mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 01:36:47 +07:00
99c6bcf46d
More multiplatform enablement for ARM platforms. The ones converted in this branch are: - bcm2835 - cns3xxx - sirf - nomadik - msx - spear - tegra - ux500 We're getting close to having most of them converted! One of the larger platforms remaining is Samsung Exynos, and there are a bunch of supporting patches in this merge window for it. There was a patch in this branch to a early version of multiplatform conversion, but it ended up being reverted due to need of more bake time. The revert commit is part of the branch since it would have required rebasing multiple dependent branches and they were stable by then. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRgg99AAoJEIwa5zzehBx3n78P/j0w/8v+F4dM29ba5M/tqbFI e3wpeFykZ/HJH+FFIEYfIablpfHsLB0LEMh0dZmwHESFC6eR0RfGL2jOkpfcH9Ne 7B/JIFN4l1iwqqKCXf+QbYL6e8YFxlJkg6BIB4KhNgliQoO/ASP/8EbcgROYuxmN KPVdw9laUCCvb5Ogh2NWVAkBHhVGAEiqK20r4TQz8alI8RUmMleWM3o+wLBWVhOO d3gtYSfuFSbrJfbpKSdycLizoV/NekdOC1A9Ov9YuOdw8DzNbrThCRQtu0tIUgxN JjfnGlEJLsJS9SESfr8SYWxTuhe/lB2dGqjQPvRtl2HGBhbtTlnWfQ0k2ZHdeJuD J50SLrGA2gN9E5PlHJXjYk8uhhGIq8bNTJ//CtDkfKTq1D7PuHVEpEctsaz3BBbM U+x9zP2v4FB+yrZu8w+gkQY/wDgHsxj08mT6BK0+l8ePdyQV22CvwmM5XlJFI03x 5J0nLYiYfef+ZN9rGgVrQbn+yv+IEkE4DmeiscjeVJE5LVdVrDpYGfx7UA7V0UA7 i3KRVpNKuy1v7GJDnKlEBPkmB+vgXTRXUPDVCuC4n0Hi5PYj4es1gY6AoXGF90wm vtKxGr/2XDLP7Ro+m0OXMttSgQShnmbrbOngfkWcFwUmG7cB3SSUUOGKM+2LNnXM MJTqVhPjkZ2GYBi/J6S/ =4hSo -----END PGP SIGNATURE----- Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform updates from Olof Johansson: "More multiplatform enablement for ARM platforms. The ones converted in this branch are: - bcm2835 - cns3xxx - sirf - nomadik - msx - spear - tegra - ux500 We're getting close to having most of them converted! One of the larger platforms remaining is Samsung Exynos, and there are a bunch of supporting patches in this merge window for it. There was a patch in this branch to a early version of multiplatform conversion, but it ended up being reverted due to need of more bake time. The revert commit is part of the branch since it would have required rebasing multiple dependent branches and they were stable by then" * tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits) mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms clocksource: nomadik-mtu: fix up clocksource/timer Revert "ARM: exynos: enable multiplatform support" ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ" ARM: exynos: enable multiplatform support rtc: s3c: make header file local mtd: onenand/samsung: make regs-onenand.h file local thermal/exynos: remove unnecessary header inclusions mmc: sdhci-s3c: remove platform dependencies ARM: samsung: move mfc device definition to s5p-dev-mfc.c ARM: exynos: move debug-macro.S to include/debug/ ARM: exynos: prepare for sparse IRQ ARM: exynos: introduce EXYNOS_ATAGS symbol ARM: tegra: build assembly files with -march=armv7-a ARM: Push selects for TWD/SCU into machine entries ARM: ux500: build hotplug.o for ARMv7-a ARM: ux500: move to multiplatform ARM: ux500: make remaining headers local ARM: ux500: make irqs.h local to platform ARM: ux500: get rid of <mach/[hardware|db8500-regs].h> ...
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/* arch/arm/plat-samsung/irq-vic-timer.c
|
|
* originally part of arch/arm/plat-s3c64xx/irq.c
|
|
*
|
|
* Copyright 2008 Openmoko, Inc.
|
|
* Copyright 2008 Simtec Electronics
|
|
* Ben Dooks <ben@simtec.co.uk>
|
|
* http://armlinux.simtec.co.uk/
|
|
*
|
|
* S3C64XX - Interrupt handling
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/irqchip/chained_irq.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <mach/map.h>
|
|
#include <mach/irqs.h>
|
|
#include <plat/cpu.h>
|
|
#include <plat/irq-vic-timer.h>
|
|
#include <plat/regs-timer.h>
|
|
|
|
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_get_chip(irq);
|
|
chained_irq_enter(chip, desc);
|
|
generic_handle_irq((int)desc->irq_data.handler_data);
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
|
|
static void s3c_irq_timer_ack(struct irq_data *d)
|
|
{
|
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
|
u32 mask = (1 << 5) << (d->irq - gc->irq_base);
|
|
|
|
irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
|
|
}
|
|
|
|
/**
|
|
* s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
|
|
* @num: Number of timers to initialize
|
|
* @timer_irq: Base IRQ number to be used for the timers.
|
|
*
|
|
* Register the necessary IRQ chaining and support for the timer IRQs
|
|
* chained of the VIC.
|
|
*/
|
|
void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
|
|
{
|
|
unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
|
|
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
|
|
struct irq_chip_generic *s3c_tgc;
|
|
struct irq_chip_type *ct;
|
|
unsigned int i;
|
|
|
|
#ifdef CONFIG_ARCH_EXYNOS
|
|
if (soc_is_exynos5250()) {
|
|
pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
|
|
pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
|
|
pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
|
|
pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
|
|
pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
|
|
} else {
|
|
pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
|
|
pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
|
|
pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
|
|
pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
|
|
pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
|
|
}
|
|
#endif
|
|
s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
|
|
S3C64XX_TINT_CSTAT, handle_level_irq);
|
|
|
|
if (!s3c_tgc) {
|
|
pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
|
|
__func__, timer_irq);
|
|
return;
|
|
}
|
|
|
|
ct = s3c_tgc->chip_types;
|
|
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
|
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
|
ct->chip.irq_ack = s3c_irq_timer_ack;
|
|
irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
|
/* Clear the upper bits of the mask_cache*/
|
|
s3c_tgc->mask_cache &= 0x1f;
|
|
|
|
for (i = 0; i < num; i++, timer_irq++) {
|
|
irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
|
|
irq_set_handler_data(pirq[i], (void *)timer_irq);
|
|
}
|
|
}
|