mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 07:02:59 +07:00
68890e2094
Every SPI transfer could have a different clock rate. The spi-geni-qcom controller code to deal with this was never very well optimized and has always had a lot of code plus some calls into the clk framework which, at the very least, would grab a mutex. However, until recently, the overhead wasn't _too_ much. That changed with commit0e3b8a81f5
("spi: spi-geni-qcom: Add interconnect support") we're now calling geni_icc_set_bw(), which leads to a bunch of math plus: geni_icc_set_bw() icc_set_bw() apply_constraints() qcom_icc_set() qcom_icc_bcm_voter_commit() rpmh_invalidate() rpmh_write_batch() ...and those rpmh commands can be a bit beefy if you call them too often. We already know what speed we were running at before, so if we see that nothing has changed let's avoid the whole pile of code. On my hardware, this made spi_geni_prepare_message() drop down from ~145 us down to ~14 us. NOTE: Potentially it might also make sense to add some code into the interconnect framework to avoid executing so much code when bandwidth isn't changing, but even if we did that we still want to short circuit here to save the extra math / clock calls. Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Akash Asthana<akashast@codeaurora.org> Fixes:0e3b8a81f5
("spi: spi-geni-qcom: Add interconnect support") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200701174506.1.Icfdcee14649fc0a6c38e87477b28523d4e60bab3@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
737 lines
19 KiB
C
737 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/qcom-geni-se.h>
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#include <linux/spi/spi.h>
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#include <linux/spinlock.h>
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/* SPI SE specific registers and respective register fields */
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#define SE_SPI_CPHA 0x224
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#define CPHA BIT(0)
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#define SE_SPI_LOOPBACK 0x22c
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#define LOOPBACK_ENABLE 0x1
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#define NORMAL_MODE 0x0
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#define LOOPBACK_MSK GENMASK(1, 0)
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#define SE_SPI_CPOL 0x230
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#define CPOL BIT(2)
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#define SE_SPI_DEMUX_OUTPUT_INV 0x24c
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#define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
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#define SE_SPI_DEMUX_SEL 0x250
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#define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
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#define SE_SPI_TRANS_CFG 0x25c
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#define CS_TOGGLE BIT(0)
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#define SE_SPI_WORD_LEN 0x268
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#define WORD_LEN_MSK GENMASK(9, 0)
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#define MIN_WORD_LEN 4
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#define SE_SPI_TX_TRANS_LEN 0x26c
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#define SE_SPI_RX_TRANS_LEN 0x270
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#define TRANS_LEN_MSK GENMASK(23, 0)
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#define SE_SPI_PRE_POST_CMD_DLY 0x274
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#define SE_SPI_DELAY_COUNTERS 0x278
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#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
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#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
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#define SPI_CS_CLK_DELAY_SHFT 10
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/* M_CMD OP codes for SPI */
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#define SPI_TX_ONLY 1
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#define SPI_RX_ONLY 2
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#define SPI_FULL_DUPLEX 3
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#define SPI_TX_RX 7
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#define SPI_CS_ASSERT 8
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#define SPI_CS_DEASSERT 9
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#define SPI_SCK_ONLY 10
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/* M_CMD params for SPI */
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#define SPI_PRE_CMD_DELAY BIT(0)
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#define TIMESTAMP_BEFORE BIT(1)
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#define FRAGMENTATION BIT(2)
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#define TIMESTAMP_AFTER BIT(3)
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#define POST_CMD_DELAY BIT(4)
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enum spi_m_cmd_opcode {
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CMD_NONE,
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CMD_XFER,
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CMD_CS,
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CMD_CANCEL,
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};
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struct spi_geni_master {
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struct geni_se se;
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struct device *dev;
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u32 tx_fifo_depth;
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u32 fifo_width_bits;
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u32 tx_wm;
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unsigned long cur_speed_hz;
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unsigned int cur_bits_per_word;
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unsigned int tx_rem_bytes;
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unsigned int rx_rem_bytes;
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const struct spi_transfer *cur_xfer;
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struct completion xfer_done;
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unsigned int oversampling;
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spinlock_t lock;
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enum spi_m_cmd_opcode cur_mcmd;
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int irq;
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};
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static int get_spi_clk_cfg(unsigned int speed_hz,
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struct spi_geni_master *mas,
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unsigned int *clk_idx,
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unsigned int *clk_div)
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{
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unsigned long sclk_freq;
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unsigned int actual_hz;
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int ret;
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ret = geni_se_clk_freq_match(&mas->se,
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speed_hz * mas->oversampling,
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clk_idx, &sclk_freq, false);
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if (ret) {
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dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
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ret, speed_hz);
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return ret;
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}
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*clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
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actual_hz = sclk_freq / (mas->oversampling * *clk_div);
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dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
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actual_hz, sclk_freq, *clk_idx, *clk_div);
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ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
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if (ret)
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dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
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return ret;
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}
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static void handle_fifo_timeout(struct spi_master *spi,
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struct spi_message *msg)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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unsigned long time_left, flags;
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struct geni_se *se = &mas->se;
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spin_lock_irqsave(&mas->lock, flags);
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reinit_completion(&mas->xfer_done);
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mas->cur_mcmd = CMD_CANCEL;
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geni_se_cancel_m_cmd(se);
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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spin_unlock_irqrestore(&mas->lock, flags);
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time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
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if (time_left)
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return;
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spin_lock_irqsave(&mas->lock, flags);
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reinit_completion(&mas->xfer_done);
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geni_se_abort_m_cmd(se);
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spin_unlock_irqrestore(&mas->lock, flags);
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time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
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if (!time_left)
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dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
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}
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static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
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struct spi_master *spi = dev_get_drvdata(mas->dev);
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struct geni_se *se = &mas->se;
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unsigned long time_left;
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reinit_completion(&mas->xfer_done);
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pm_runtime_get_sync(mas->dev);
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if (!(slv->mode & SPI_CS_HIGH))
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set_flag = !set_flag;
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mas->cur_mcmd = CMD_CS;
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if (set_flag)
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geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
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else
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geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
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time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
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if (!time_left)
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handle_fifo_timeout(spi, NULL);
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pm_runtime_put(mas->dev);
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}
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static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
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unsigned int bits_per_word)
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{
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unsigned int pack_words;
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bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
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struct geni_se *se = &mas->se;
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u32 word_len;
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word_len = readl(se->base + SE_SPI_WORD_LEN);
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/*
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* If bits_per_word isn't a byte aligned value, set the packing to be
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* 1 SPI word per FIFO word.
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*/
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if (!(mas->fifo_width_bits % bits_per_word))
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pack_words = mas->fifo_width_bits / bits_per_word;
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else
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pack_words = 1;
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word_len &= ~WORD_LEN_MSK;
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word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK);
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geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
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true, true);
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writel(word_len, se->base + SE_SPI_WORD_LEN);
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}
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static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
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unsigned long clk_hz)
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{
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u32 clk_sel, m_clk_cfg, idx, div;
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struct geni_se *se = &mas->se;
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int ret;
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if (clk_hz == mas->cur_speed_hz)
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return 0;
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ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
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if (ret) {
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dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
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return ret;
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}
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/*
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* SPI core clock gets configured with the requested frequency
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* or the frequency closer to the requested frequency.
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* For that reason requested frequency is stored in the
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* cur_speed_hz and referred in the consecutive transfer instead
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* of calling clk_get_rate() API.
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*/
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mas->cur_speed_hz = clk_hz;
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clk_sel = idx & CLK_SEL_MSK;
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m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
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writel(clk_sel, se->base + SE_GENI_CLK_SEL);
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writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
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/* Set BW quota for CPU as driver supports FIFO mode only. */
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se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
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ret = geni_icc_set_bw(se);
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if (ret)
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return ret;
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return 0;
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}
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static int setup_fifo_params(struct spi_device *spi_slv,
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struct spi_master *spi)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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struct geni_se *se = &mas->se;
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u32 loopback_cfg, cpol, cpha, demux_output_inv;
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u32 demux_sel;
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loopback_cfg = readl(se->base + SE_SPI_LOOPBACK);
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cpol = readl(se->base + SE_SPI_CPOL);
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cpha = readl(se->base + SE_SPI_CPHA);
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demux_output_inv = 0;
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loopback_cfg &= ~LOOPBACK_MSK;
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cpol &= ~CPOL;
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cpha &= ~CPHA;
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if (spi_slv->mode & SPI_LOOP)
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loopback_cfg |= LOOPBACK_ENABLE;
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if (spi_slv->mode & SPI_CPOL)
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cpol |= CPOL;
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if (spi_slv->mode & SPI_CPHA)
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cpha |= CPHA;
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if (spi_slv->mode & SPI_CS_HIGH)
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demux_output_inv = BIT(spi_slv->chip_select);
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demux_sel = spi_slv->chip_select;
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mas->cur_bits_per_word = spi_slv->bits_per_word;
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spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
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writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
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writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
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writel(cpha, se->base + SE_SPI_CPHA);
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writel(cpol, se->base + SE_SPI_CPOL);
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writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
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return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
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}
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static int spi_geni_prepare_message(struct spi_master *spi,
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struct spi_message *spi_msg)
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{
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int ret;
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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struct geni_se *se = &mas->se;
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geni_se_select_mode(se, GENI_SE_FIFO);
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ret = setup_fifo_params(spi_msg->spi, spi);
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if (ret)
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dev_err(mas->dev, "Couldn't select mode %d\n", ret);
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return ret;
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}
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static int spi_geni_init(struct spi_geni_master *mas)
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{
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struct geni_se *se = &mas->se;
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unsigned int proto, major, minor, ver;
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pm_runtime_get_sync(mas->dev);
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proto = geni_se_read_proto(se);
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if (proto != GENI_SE_SPI) {
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dev_err(mas->dev, "Invalid proto %d\n", proto);
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pm_runtime_put(mas->dev);
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return -ENXIO;
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}
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mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
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/* Width of Tx and Rx FIFO is same */
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mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
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/*
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* Hardware programming guide suggests to configure
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* RX FIFO RFR level to fifo_depth-2.
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*/
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geni_se_init(se, 0x0, mas->tx_fifo_depth - 2);
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/* Transmit an entire FIFO worth of data per IRQ */
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mas->tx_wm = 1;
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ver = geni_se_get_qup_hw_version(se);
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major = GENI_SE_VERSION_MAJOR(ver);
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minor = GENI_SE_VERSION_MINOR(ver);
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if (major == 1 && minor == 0)
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mas->oversampling = 2;
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else
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mas->oversampling = 1;
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pm_runtime_put(mas->dev);
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return 0;
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}
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static void setup_fifo_xfer(struct spi_transfer *xfer,
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struct spi_geni_master *mas,
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u16 mode, struct spi_master *spi)
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{
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u32 m_cmd = 0;
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u32 spi_tx_cfg, len;
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struct geni_se *se = &mas->se;
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int ret;
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spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
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if (xfer->bits_per_word != mas->cur_bits_per_word) {
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spi_setup_word_len(mas, mode, xfer->bits_per_word);
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mas->cur_bits_per_word = xfer->bits_per_word;
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}
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/* Speed and bits per word can be overridden per transfer */
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ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
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if (ret)
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return;
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mas->tx_rem_bytes = 0;
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mas->rx_rem_bytes = 0;
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if (xfer->tx_buf && xfer->rx_buf)
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m_cmd = SPI_FULL_DUPLEX;
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else if (xfer->tx_buf)
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m_cmd = SPI_TX_ONLY;
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else if (xfer->rx_buf)
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m_cmd = SPI_RX_ONLY;
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spi_tx_cfg &= ~CS_TOGGLE;
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if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
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len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
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else
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len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
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len &= TRANS_LEN_MSK;
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mas->cur_xfer = xfer;
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if (m_cmd & SPI_TX_ONLY) {
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mas->tx_rem_bytes = xfer->len;
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writel(len, se->base + SE_SPI_TX_TRANS_LEN);
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}
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if (m_cmd & SPI_RX_ONLY) {
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writel(len, se->base + SE_SPI_RX_TRANS_LEN);
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mas->rx_rem_bytes = xfer->len;
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}
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writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
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mas->cur_mcmd = CMD_XFER;
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geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
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/*
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* TX_WATERMARK_REG should be set after SPI configuration and
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* setting up GENI SE engine, as driver starts data transfer
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* for the watermark interrupt.
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*/
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if (m_cmd & SPI_TX_ONLY)
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writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
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}
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static int spi_geni_transfer_one(struct spi_master *spi,
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struct spi_device *slv,
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struct spi_transfer *xfer)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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/* Terminate and return success for 0 byte length transfer */
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if (!xfer->len)
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return 0;
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setup_fifo_xfer(xfer, mas, slv->mode, spi);
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return 1;
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}
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static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
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{
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/*
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* Calculate how many bytes we'll put in each FIFO word. If the
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* transfer words don't pack cleanly into a FIFO word we'll just put
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* one transfer word in each FIFO word. If they do pack we'll pack 'em.
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*/
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if (mas->fifo_width_bits % mas->cur_bits_per_word)
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return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
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BITS_PER_BYTE));
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return mas->fifo_width_bits / BITS_PER_BYTE;
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}
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static void geni_spi_handle_tx(struct spi_geni_master *mas)
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{
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struct geni_se *se = &mas->se;
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unsigned int max_bytes;
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const u8 *tx_buf;
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unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
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unsigned int i = 0;
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max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
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if (mas->tx_rem_bytes < max_bytes)
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max_bytes = mas->tx_rem_bytes;
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tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
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while (i < max_bytes) {
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unsigned int j;
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unsigned int bytes_to_write;
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u32 fifo_word = 0;
|
|
u8 *fifo_byte = (u8 *)&fifo_word;
|
|
|
|
bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
|
|
for (j = 0; j < bytes_to_write; j++)
|
|
fifo_byte[j] = tx_buf[i++];
|
|
iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
|
|
}
|
|
mas->tx_rem_bytes -= max_bytes;
|
|
if (!mas->tx_rem_bytes)
|
|
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
|
|
}
|
|
|
|
static void geni_spi_handle_rx(struct spi_geni_master *mas)
|
|
{
|
|
struct geni_se *se = &mas->se;
|
|
u32 rx_fifo_status;
|
|
unsigned int rx_bytes;
|
|
unsigned int rx_last_byte_valid;
|
|
u8 *rx_buf;
|
|
unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
|
|
unsigned int i = 0;
|
|
|
|
rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
|
|
rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
|
|
if (rx_fifo_status & RX_LAST) {
|
|
rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
|
|
rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
|
|
if (rx_last_byte_valid && rx_last_byte_valid < 4)
|
|
rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
|
|
}
|
|
if (mas->rx_rem_bytes < rx_bytes)
|
|
rx_bytes = mas->rx_rem_bytes;
|
|
|
|
rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
|
|
while (i < rx_bytes) {
|
|
u32 fifo_word = 0;
|
|
u8 *fifo_byte = (u8 *)&fifo_word;
|
|
unsigned int bytes_to_read;
|
|
unsigned int j;
|
|
|
|
bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
|
|
ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
|
|
for (j = 0; j < bytes_to_read; j++)
|
|
rx_buf[i++] = fifo_byte[j];
|
|
}
|
|
mas->rx_rem_bytes -= rx_bytes;
|
|
}
|
|
|
|
static irqreturn_t geni_spi_isr(int irq, void *data)
|
|
{
|
|
struct spi_master *spi = data;
|
|
struct spi_geni_master *mas = spi_master_get_devdata(spi);
|
|
struct geni_se *se = &mas->se;
|
|
u32 m_irq;
|
|
unsigned long flags;
|
|
|
|
if (mas->cur_mcmd == CMD_NONE)
|
|
return IRQ_NONE;
|
|
|
|
spin_lock_irqsave(&mas->lock, flags);
|
|
m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
|
|
|
|
if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
|
|
geni_spi_handle_rx(mas);
|
|
|
|
if (m_irq & M_TX_FIFO_WATERMARK_EN)
|
|
geni_spi_handle_tx(mas);
|
|
|
|
if (m_irq & M_CMD_DONE_EN) {
|
|
if (mas->cur_mcmd == CMD_XFER)
|
|
spi_finalize_current_transfer(spi);
|
|
else if (mas->cur_mcmd == CMD_CS)
|
|
complete(&mas->xfer_done);
|
|
mas->cur_mcmd = CMD_NONE;
|
|
/*
|
|
* If this happens, then a CMD_DONE came before all the Tx
|
|
* buffer bytes were sent out. This is unusual, log this
|
|
* condition and disable the WM interrupt to prevent the
|
|
* system from stalling due an interrupt storm.
|
|
* If this happens when all Rx bytes haven't been received, log
|
|
* the condition.
|
|
* The only known time this can happen is if bits_per_word != 8
|
|
* and some registers that expect xfer lengths in num spi_words
|
|
* weren't written correctly.
|
|
*/
|
|
if (mas->tx_rem_bytes) {
|
|
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
|
|
dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
|
|
mas->tx_rem_bytes, mas->cur_bits_per_word);
|
|
}
|
|
if (mas->rx_rem_bytes)
|
|
dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
|
|
mas->rx_rem_bytes, mas->cur_bits_per_word);
|
|
}
|
|
|
|
if ((m_irq & M_CMD_CANCEL_EN) || (m_irq & M_CMD_ABORT_EN)) {
|
|
mas->cur_mcmd = CMD_NONE;
|
|
complete(&mas->xfer_done);
|
|
}
|
|
|
|
writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
|
|
spin_unlock_irqrestore(&mas->lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int spi_geni_probe(struct platform_device *pdev)
|
|
{
|
|
int ret, irq;
|
|
struct spi_master *spi;
|
|
struct spi_geni_master *mas;
|
|
void __iomem *base;
|
|
struct clk *clk;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
clk = devm_clk_get(dev, "se");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
spi = spi_alloc_master(dev, sizeof(*mas));
|
|
if (!spi)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, spi);
|
|
mas = spi_master_get_devdata(spi);
|
|
mas->irq = irq;
|
|
mas->dev = dev;
|
|
mas->se.dev = dev;
|
|
mas->se.wrapper = dev_get_drvdata(dev->parent);
|
|
mas->se.base = base;
|
|
mas->se.clk = clk;
|
|
mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
|
|
if (IS_ERR(mas->se.opp_table))
|
|
return PTR_ERR(mas->se.opp_table);
|
|
/* OPP table is optional */
|
|
ret = dev_pm_opp_of_add_table(&pdev->dev);
|
|
if (!ret) {
|
|
mas->se.has_opp_table = true;
|
|
} else if (ret != -ENODEV) {
|
|
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
|
|
return ret;
|
|
}
|
|
|
|
spi->bus_num = -1;
|
|
spi->dev.of_node = dev->of_node;
|
|
spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
|
|
spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
|
spi->num_chipselect = 4;
|
|
spi->max_speed_hz = 50000000;
|
|
spi->prepare_message = spi_geni_prepare_message;
|
|
spi->transfer_one = spi_geni_transfer_one;
|
|
spi->auto_runtime_pm = true;
|
|
spi->handle_err = handle_fifo_timeout;
|
|
spi->set_cs = spi_geni_set_cs;
|
|
|
|
init_completion(&mas->xfer_done);
|
|
spin_lock_init(&mas->lock);
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = geni_icc_get(&mas->se, NULL);
|
|
if (ret)
|
|
goto spi_geni_probe_runtime_disable;
|
|
/* Set the bus quota to a reasonable value for register access */
|
|
mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
|
|
mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
|
|
|
|
ret = geni_icc_set_bw(&mas->se);
|
|
if (ret)
|
|
goto spi_geni_probe_runtime_disable;
|
|
|
|
ret = spi_geni_init(mas);
|
|
if (ret)
|
|
goto spi_geni_probe_runtime_disable;
|
|
|
|
ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
|
|
if (ret)
|
|
goto spi_geni_probe_runtime_disable;
|
|
|
|
ret = spi_register_master(spi);
|
|
if (ret)
|
|
goto spi_geni_probe_free_irq;
|
|
|
|
return 0;
|
|
spi_geni_probe_free_irq:
|
|
free_irq(mas->irq, spi);
|
|
spi_geni_probe_runtime_disable:
|
|
pm_runtime_disable(dev);
|
|
spi_master_put(spi);
|
|
if (mas->se.has_opp_table)
|
|
dev_pm_opp_of_remove_table(&pdev->dev);
|
|
dev_pm_opp_put_clkname(mas->se.opp_table);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_geni_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *spi = platform_get_drvdata(pdev);
|
|
struct spi_geni_master *mas = spi_master_get_devdata(spi);
|
|
|
|
/* Unregister _before_ disabling pm_runtime() so we stop transfers */
|
|
spi_unregister_master(spi);
|
|
|
|
free_irq(mas->irq, spi);
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (mas->se.has_opp_table)
|
|
dev_pm_opp_of_remove_table(&pdev->dev);
|
|
dev_pm_opp_put_clkname(mas->se.opp_table);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *spi = dev_get_drvdata(dev);
|
|
struct spi_geni_master *mas = spi_master_get_devdata(spi);
|
|
int ret;
|
|
|
|
/* Drop the performance state vote */
|
|
dev_pm_opp_set_rate(dev, 0);
|
|
|
|
ret = geni_se_resources_off(&mas->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return geni_icc_disable(&mas->se);
|
|
}
|
|
|
|
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *spi = dev_get_drvdata(dev);
|
|
struct spi_geni_master *mas = spi_master_get_devdata(spi);
|
|
int ret;
|
|
|
|
ret = geni_icc_enable(&mas->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return geni_se_resources_on(&mas->se);
|
|
}
|
|
|
|
static int __maybe_unused spi_geni_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *spi = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = spi_master_suspend(spi);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_force_suspend(dev);
|
|
if (ret)
|
|
spi_master_resume(spi);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused spi_geni_resume(struct device *dev)
|
|
{
|
|
struct spi_master *spi = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_force_resume(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = spi_master_resume(spi);
|
|
if (ret)
|
|
pm_runtime_force_suspend(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops spi_geni_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
|
|
spi_geni_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
|
|
};
|
|
|
|
static const struct of_device_id spi_geni_dt_match[] = {
|
|
{ .compatible = "qcom,geni-spi" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
|
|
|
|
static struct platform_driver spi_geni_driver = {
|
|
.probe = spi_geni_probe,
|
|
.remove = spi_geni_remove,
|
|
.driver = {
|
|
.name = "geni_spi",
|
|
.pm = &spi_geni_pm_ops,
|
|
.of_match_table = spi_geni_dt_match,
|
|
},
|
|
};
|
|
module_platform_driver(spi_geni_driver);
|
|
|
|
MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
|
|
MODULE_LICENSE("GPL v2");
|