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0efa7579f3
caam/qi2 driver will support ahash algorithms, thus move ahash descriptors generation in a shared location. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
22 lines
691 B
C
22 lines
691 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Shared descriptors for ahash algorithms
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*
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* Copyright 2017 NXP
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*/
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#ifndef _CAAMHASH_DESC_H_
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#define _CAAMHASH_DESC_H_
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/* length of descriptors text */
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#define DESC_AHASH_BASE (3 * CAAM_CMD_SZ)
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#define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ)
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#define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
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#define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
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#define DESC_AHASH_DIGEST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
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void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
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int digestsize, int ctx_len, bool import_ctx, int era);
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#endif /* _CAAMHASH_DESC_H_ */
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