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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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12de44f55d
The FEC driver ignores the GPIO polarity from 'phy-reset-gpios' and considers that the Ethernet PHY is active low, unless the property 'phy-reset-active-high' is present. Fix the device tree description by explicitly passing the 'GPIO_ACTIVE_LOW' flag to the 'phy-reset-gpios' property. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
272 lines
6.5 KiB
Plaintext
272 lines
6.5 KiB
Plaintext
/*
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* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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#include "imx6ul-tx6ul.dtsi"
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/ {
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model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
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compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
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aliases {
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lcdif_24bit_pins_a = &pinctrl_disp0_3;
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mmc0 = &usdhc1;
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/delete-property/ mmc1;
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serial2 = &uart3;
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serial4 = &uart5;
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};
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/delete-node/ sound;
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};
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&can1 {
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xceiver-supply = <®_3v3>;
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};
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&can2 {
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xceiver-supply = <®_3v3>;
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};
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&ds1339 {
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status = "disabled";
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};
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&fec1 {
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
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/delete-node/ mdio;
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
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phy-supply = <®_3v3_etn>;
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phy-handle = <&etnphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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etnphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy0_int>;
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interrupt-parent = <&gpio5>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
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status = "okay";
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};
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etnphy1: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy1_int>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>;
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status = "okay";
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};
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};
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};
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&i2c_gpio {
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status = "disabled";
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};
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&i2c2 {
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/delete-node/ codec@0a;
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/delete-node/ touchscreen@48;
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rtc: mcp7940x@6f {
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compatible = "microchip,mcp7940x";
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reg = <0x6f>;
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};
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};
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&kpp {
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status = "disabled";
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};
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&lcdif {
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pinctrl-0 = <&pinctrl_disp0_3>;
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};
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®_usbotg_vbus{
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status = "disabled";
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};
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&usdhc1 {
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pinctrl-0 = <&pinctrl_usdhc1>;
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non-removable;
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/delete-property/ cd-gpios;
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cap-sdio-irq;
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};
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&uart1 {
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pinctrl-0 = <&pinctrl_uart1>;
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/delete-property/ uart-has-rtscts;
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};
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&uart2 {
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pinctrl-0 = <&pinctrl_uart2>;
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/delete-property/ uart-has-rtscts;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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status = "okay";
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};
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&uart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6>;
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status = "okay";
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};
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&uart7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart7>;
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status = "okay";
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};
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&uart8 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart8>;
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status = "disabled"; /* conflicts with LCDIF */
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};
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&iomuxc {
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hoggrp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */
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>;
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};
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pinctrl_disp0_3: disp0grp-3 {
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fsl,pins = <
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MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
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MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
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MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
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MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
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/* LCD_DATA08..09 not wired */
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
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MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
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/* LCD_DATA16..17 not wired */
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MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
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MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
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MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
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MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
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MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
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MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
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>;
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};
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pinctrl_enet2_mdio: enet2-mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0
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MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0
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MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0
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>;
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};
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pinctrl_uart6: uart6grp {
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fsl,pins = <
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MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0
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MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0
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>;
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};
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pinctrl_uart7: uart7grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0
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MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0
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>;
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};
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pinctrl_uart8: uart8grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0
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MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0
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>;
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};
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};
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