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a20f997010
By default, DSA drivers should configure CPU and DSA ports to their
maximum speed. In many configurations this is sufficient to make the
link work.
In some cases it is necessary to configure the link to run slower,
e.g. because of limitations of the SoC it is connected to. Or back to
back PHYs are used and the PHY needs to be driven in order to
establish link. In this case, phylink is used.
Only instantiate phylink if it is required. If there is no PHY, or no
fixed link properties, phylink can upset a link which works in the
default configuration.
Fixes:
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.. | ||
dsa2.c | ||
dsa_priv.h | ||
dsa.c | ||
Kconfig | ||
Makefile | ||
master.c | ||
port.c | ||
slave.c | ||
switch.c | ||
tag_8021q.c | ||
tag_ar9331.c | ||
tag_brcm.c | ||
tag_dsa.c | ||
tag_edsa.c | ||
tag_gswip.c | ||
tag_ksz.c | ||
tag_lan9303.c | ||
tag_mtk.c | ||
tag_ocelot.c | ||
tag_qca.c | ||
tag_sja1105.c | ||
tag_trailer.c |