mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 13:06:45 +07:00
9a9952bbd7
This time the IOMMU updates are mostly cleanups or fixes. No big new
features or drivers this time. In particular the changes include:
* Bigger cleanup of the Domain<->IOMMU data structures and the
code that manages them in the Intel VT-d driver. This makes
the code easier to understand and maintain, and also easier to
keep the data structures in sync. It is also a preparation
step to make use of default domains from the IOMMU core in the
Intel VT-d driver.
* Fixes for a couple of DMA-API misuses in ARM IOMMU drivers,
namely in the ARM and Tegra SMMU drivers.
* Fix for a potential buffer overflow in the OMAP iommu driver's
debug code
* A couple of smaller fixes and cleanups in various drivers
* One small new feature: Report domain-id usage in the Intel
VT-d driver to easier detect bugs where these are leaked.
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Merge tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates for from Joerg Roedel:
"This time the IOMMU updates are mostly cleanups or fixes. No big new
features or drivers this time. In particular the changes include:
- Bigger cleanup of the Domain<->IOMMU data structures and the code
that manages them in the Intel VT-d driver. This makes the code
easier to understand and maintain, and also easier to keep the data
structures in sync. It is also a preparation step to make use of
default domains from the IOMMU core in the Intel VT-d driver.
- Fixes for a couple of DMA-API misuses in ARM IOMMU drivers, namely
in the ARM and Tegra SMMU drivers.
- Fix for a potential buffer overflow in the OMAP iommu driver's
debug code
- A couple of smaller fixes and cleanups in various drivers
- One small new feature: Report domain-id usage in the Intel VT-d
driver to easier detect bugs where these are leaked"
* tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (83 commits)
iommu/vt-d: Really use upper context table when necessary
x86/vt-d: Fix documentation of DRHD
iommu/fsl: Really fix init section(s) content
iommu/io-pgtable-arm: Unmap and free table when overwriting with block
iommu/io-pgtable-arm: Move init-fn declarations to io-pgtable.h
iommu/msm: Use BUG_ON instead of if () BUG()
iommu/vt-d: Access iomem correctly
iommu/vt-d: Make two functions static
iommu/vt-d: Use BUG_ON instead of if () BUG()
iommu/vt-d: Return false instead of 0 in irq_remapping_cap()
iommu/amd: Use BUG_ON instead of if () BUG()
iommu/amd: Make a symbol static
iommu/amd: Simplify allocation in irq_remapping_alloc()
iommu/tegra-smmu: Parameterize number of TLB lines
iommu/tegra-smmu: Factor out tegra_smmu_set_pde()
iommu/tegra-smmu: Extract tegra_smmu_pte_get_use()
iommu/tegra-smmu: Use __GFP_ZERO to allocate zeroed pages
iommu/tegra-smmu: Remove PageReserved manipulation
iommu/tegra-smmu: Convert to use DMA API
iommu/tegra-smmu: smmu_flush_ptc() wants device addresses
...
956 lines
15 KiB
C
956 lines
15 KiB
C
/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of.h>
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#include <linux/mm.h>
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#include <dt-bindings/memory/tegra30-mc.h>
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#include "mc.h"
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static const struct tegra_mc_client tegra30_mc_clients[] = {
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{
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.id = 0x00,
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.name = "ptcr",
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.swgroup = TEGRA_SWGROUP_PTC,
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}, {
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.id = 0x01,
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.name = "display0a",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 1,
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},
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.la = {
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.reg = 0x2e8,
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.shift = 0,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x02,
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.name = "display0ab",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 2,
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},
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.la = {
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.reg = 0x2f4,
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.shift = 0,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x03,
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.name = "display0b",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 3,
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},
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.la = {
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.reg = 0x2e8,
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.shift = 16,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x04,
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.name = "display0bb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 4,
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},
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.la = {
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.reg = 0x2f4,
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.shift = 16,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x05,
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.name = "display0c",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 5,
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},
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.la = {
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.reg = 0x2ec,
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.shift = 0,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x06,
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.name = "display0cb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 6,
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},
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.la = {
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.reg = 0x2f8,
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.shift = 0,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x07,
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.name = "display1b",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 7,
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},
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.la = {
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.reg = 0x2ec,
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.shift = 16,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x08,
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.name = "display1bb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 8,
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},
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.la = {
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.reg = 0x2f8,
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.shift = 16,
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.mask = 0xff,
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.def = 0x4e,
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},
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}, {
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.id = 0x09,
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.name = "eppup",
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.swgroup = TEGRA_SWGROUP_EPP,
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.smmu = {
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.reg = 0x228,
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.bit = 9,
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},
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.la = {
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.reg = 0x300,
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.shift = 0,
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.mask = 0xff,
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.def = 0x17,
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},
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}, {
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.id = 0x0a,
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.name = "g2pr",
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.swgroup = TEGRA_SWGROUP_G2,
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.smmu = {
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.reg = 0x228,
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.bit = 10,
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},
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.la = {
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.reg = 0x308,
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.shift = 0,
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.mask = 0xff,
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.def = 0x09,
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},
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}, {
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.id = 0x0b,
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.name = "g2sr",
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.swgroup = TEGRA_SWGROUP_G2,
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.smmu = {
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.reg = 0x228,
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.bit = 11,
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},
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.la = {
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.reg = 0x308,
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.shift = 16,
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.mask = 0xff,
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.def = 0x09,
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},
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}, {
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.id = 0x0c,
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.name = "mpeunifbr",
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.swgroup = TEGRA_SWGROUP_MPE,
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.smmu = {
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.reg = 0x228,
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.bit = 12,
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},
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.la = {
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.reg = 0x328,
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.shift = 0,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x0d,
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.name = "viruv",
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.swgroup = TEGRA_SWGROUP_VI,
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.smmu = {
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.reg = 0x228,
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.bit = 13,
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},
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.la = {
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.reg = 0x364,
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.shift = 0,
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.mask = 0xff,
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.def = 0x2c,
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},
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}, {
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.id = 0x0e,
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.name = "afir",
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.swgroup = TEGRA_SWGROUP_AFI,
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.smmu = {
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.reg = 0x228,
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.bit = 14,
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},
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.la = {
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.reg = 0x2e0,
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.shift = 0,
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.mask = 0xff,
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.def = 0x10,
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},
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}, {
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.id = 0x0f,
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.name = "avpcarm7r",
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.swgroup = TEGRA_SWGROUP_AVPC,
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.smmu = {
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.reg = 0x228,
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.bit = 15,
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},
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.la = {
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.reg = 0x2e4,
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.shift = 0,
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.mask = 0xff,
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.def = 0x04,
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},
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}, {
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.id = 0x10,
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.name = "displayhc",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 16,
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},
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.la = {
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.reg = 0x2f0,
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.shift = 0,
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.mask = 0xff,
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.def = 0xff,
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},
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}, {
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.id = 0x11,
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.name = "displayhcb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 17,
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},
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.la = {
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.reg = 0x2fc,
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.shift = 0,
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.mask = 0xff,
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.def = 0xff,
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},
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}, {
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.id = 0x12,
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.name = "fdcdrd",
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.swgroup = TEGRA_SWGROUP_NV,
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.smmu = {
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.reg = 0x228,
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.bit = 18,
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},
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.la = {
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.reg = 0x334,
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.shift = 0,
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.mask = 0xff,
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.def = 0x0a,
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},
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}, {
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.id = 0x13,
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.name = "fdcdrd2",
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.swgroup = TEGRA_SWGROUP_NV2,
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.smmu = {
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.reg = 0x228,
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.bit = 19,
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},
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.la = {
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.reg = 0x33c,
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.shift = 0,
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.mask = 0xff,
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.def = 0x0a,
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},
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}, {
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.id = 0x14,
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.name = "g2dr",
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.swgroup = TEGRA_SWGROUP_G2,
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.smmu = {
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.reg = 0x228,
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.bit = 20,
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},
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.la = {
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.reg = 0x30c,
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.shift = 0,
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.mask = 0xff,
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.def = 0x0a,
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},
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}, {
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.id = 0x15,
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.name = "hdar",
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.swgroup = TEGRA_SWGROUP_HDA,
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.smmu = {
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.reg = 0x228,
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.bit = 21,
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},
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.la = {
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.reg = 0x318,
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.shift = 0,
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.mask = 0xff,
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.def = 0xff,
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},
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}, {
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.id = 0x16,
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.name = "host1xdmar",
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.swgroup = TEGRA_SWGROUP_HC,
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.smmu = {
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.reg = 0x228,
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.bit = 22,
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},
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.la = {
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.reg = 0x310,
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.shift = 0,
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.mask = 0xff,
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.def = 0x05,
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},
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}, {
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.id = 0x17,
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.name = "host1xr",
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.swgroup = TEGRA_SWGROUP_HC,
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.smmu = {
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.reg = 0x228,
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.bit = 23,
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},
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.la = {
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.reg = 0x310,
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.shift = 16,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x18,
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.name = "idxsrd",
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.swgroup = TEGRA_SWGROUP_NV,
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.smmu = {
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.reg = 0x228,
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.bit = 24,
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},
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.la = {
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.reg = 0x334,
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.shift = 16,
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.mask = 0xff,
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.def = 0x13,
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},
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}, {
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.id = 0x19,
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.name = "idxsrd2",
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.swgroup = TEGRA_SWGROUP_NV2,
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.smmu = {
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.reg = 0x228,
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.bit = 25,
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},
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.la = {
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.reg = 0x33c,
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.shift = 16,
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.mask = 0xff,
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.def = 0x13,
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},
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}, {
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.id = 0x1a,
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.name = "mpe_ipred",
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.swgroup = TEGRA_SWGROUP_MPE,
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.smmu = {
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.reg = 0x228,
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.bit = 26,
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},
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.la = {
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.reg = 0x328,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x1b,
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.name = "mpeamemrd",
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.swgroup = TEGRA_SWGROUP_MPE,
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.smmu = {
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.reg = 0x228,
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.bit = 27,
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},
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.la = {
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.reg = 0x32c,
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.shift = 0,
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.mask = 0xff,
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.def = 0x42,
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},
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}, {
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.id = 0x1c,
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.name = "mpecsrd",
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.swgroup = TEGRA_SWGROUP_MPE,
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.smmu = {
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.reg = 0x228,
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.bit = 28,
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},
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.la = {
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.reg = 0x32c,
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.shift = 16,
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.mask = 0xff,
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.def = 0xff,
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},
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}, {
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.id = 0x1d,
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.name = "ppcsahbdmar",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x228,
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.bit = 29,
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},
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.la = {
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.reg = 0x344,
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.shift = 0,
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.mask = 0xff,
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.def = 0x10,
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},
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}, {
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.id = 0x1e,
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.name = "ppcsahbslvr",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x228,
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.bit = 30,
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},
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.la = {
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.reg = 0x344,
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.shift = 16,
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.mask = 0xff,
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.def = 0x12,
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},
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}, {
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.id = 0x1f,
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.name = "satar",
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.swgroup = TEGRA_SWGROUP_SATA,
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.smmu = {
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.reg = 0x228,
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.bit = 31,
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},
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.la = {
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.reg = 0x350,
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.shift = 0,
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.mask = 0xff,
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.def = 0x33,
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},
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}, {
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.id = 0x20,
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.name = "texsrd",
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.swgroup = TEGRA_SWGROUP_NV,
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.smmu = {
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.reg = 0x22c,
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.bit = 0,
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},
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.la = {
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.reg = 0x338,
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.shift = 0,
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.mask = 0xff,
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.def = 0x13,
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},
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}, {
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.id = 0x21,
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.name = "texsrd2",
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.swgroup = TEGRA_SWGROUP_NV2,
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.smmu = {
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.reg = 0x22c,
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.bit = 1,
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},
|
|
.la = {
|
|
.reg = 0x340,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x13,
|
|
},
|
|
}, {
|
|
.id = 0x22,
|
|
.name = "vdebsevr",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 2,
|
|
},
|
|
.la = {
|
|
.reg = 0x354,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x23,
|
|
.name = "vdember",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 3,
|
|
},
|
|
.la = {
|
|
.reg = 0x354,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0xd0,
|
|
},
|
|
}, {
|
|
.id = 0x24,
|
|
.name = "vdemcer",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 4,
|
|
},
|
|
.la = {
|
|
.reg = 0x358,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x2a,
|
|
},
|
|
}, {
|
|
.id = 0x25,
|
|
.name = "vdetper",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 5,
|
|
},
|
|
.la = {
|
|
.reg = 0x358,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x74,
|
|
},
|
|
}, {
|
|
.id = 0x26,
|
|
.name = "mpcorelpr",
|
|
.swgroup = TEGRA_SWGROUP_MPCORELP,
|
|
.la = {
|
|
.reg = 0x324,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x04,
|
|
},
|
|
}, {
|
|
.id = 0x27,
|
|
.name = "mpcorer",
|
|
.swgroup = TEGRA_SWGROUP_MPCORE,
|
|
.la = {
|
|
.reg = 0x320,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x04,
|
|
},
|
|
}, {
|
|
.id = 0x28,
|
|
.name = "eppu",
|
|
.swgroup = TEGRA_SWGROUP_EPP,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 8,
|
|
},
|
|
.la = {
|
|
.reg = 0x300,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x6c,
|
|
},
|
|
}, {
|
|
.id = 0x29,
|
|
.name = "eppv",
|
|
.swgroup = TEGRA_SWGROUP_EPP,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 9,
|
|
},
|
|
.la = {
|
|
.reg = 0x304,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x6c,
|
|
},
|
|
}, {
|
|
.id = 0x2a,
|
|
.name = "eppy",
|
|
.swgroup = TEGRA_SWGROUP_EPP,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 10,
|
|
},
|
|
.la = {
|
|
.reg = 0x304,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x6c,
|
|
},
|
|
}, {
|
|
.id = 0x2b,
|
|
.name = "mpeunifbw",
|
|
.swgroup = TEGRA_SWGROUP_MPE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 11,
|
|
},
|
|
.la = {
|
|
.reg = 0x330,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x13,
|
|
},
|
|
}, {
|
|
.id = 0x2c,
|
|
.name = "viwsb",
|
|
.swgroup = TEGRA_SWGROUP_VI,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 12,
|
|
},
|
|
.la = {
|
|
.reg = 0x364,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x12,
|
|
},
|
|
}, {
|
|
.id = 0x2d,
|
|
.name = "viwu",
|
|
.swgroup = TEGRA_SWGROUP_VI,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 13,
|
|
},
|
|
.la = {
|
|
.reg = 0x368,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0xb2,
|
|
},
|
|
}, {
|
|
.id = 0x2e,
|
|
.name = "viwv",
|
|
.swgroup = TEGRA_SWGROUP_VI,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 14,
|
|
},
|
|
.la = {
|
|
.reg = 0x368,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0xb2,
|
|
},
|
|
}, {
|
|
.id = 0x2f,
|
|
.name = "viwy",
|
|
.swgroup = TEGRA_SWGROUP_VI,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 15,
|
|
},
|
|
.la = {
|
|
.reg = 0x36c,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x12,
|
|
},
|
|
}, {
|
|
.id = 0x30,
|
|
.name = "g2dw",
|
|
.swgroup = TEGRA_SWGROUP_G2,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 16,
|
|
},
|
|
.la = {
|
|
.reg = 0x30c,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x9,
|
|
},
|
|
}, {
|
|
.id = 0x31,
|
|
.name = "afiw",
|
|
.swgroup = TEGRA_SWGROUP_AFI,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 17,
|
|
},
|
|
.la = {
|
|
.reg = 0x2e0,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0c,
|
|
},
|
|
}, {
|
|
.id = 0x32,
|
|
.name = "avpcarm7w",
|
|
.swgroup = TEGRA_SWGROUP_AVPC,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 18,
|
|
},
|
|
.la = {
|
|
.reg = 0x2e4,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0e,
|
|
},
|
|
}, {
|
|
.id = 0x33,
|
|
.name = "fdcdwr",
|
|
.swgroup = TEGRA_SWGROUP_NV,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 19,
|
|
},
|
|
.la = {
|
|
.reg = 0x338,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0a,
|
|
},
|
|
}, {
|
|
.id = 0x34,
|
|
.name = "fdcwr2",
|
|
.swgroup = TEGRA_SWGROUP_NV2,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 20,
|
|
},
|
|
.la = {
|
|
.reg = 0x340,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0a,
|
|
},
|
|
}, {
|
|
.id = 0x35,
|
|
.name = "hdaw",
|
|
.swgroup = TEGRA_SWGROUP_HDA,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 21,
|
|
},
|
|
.la = {
|
|
.reg = 0x318,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x36,
|
|
.name = "host1xw",
|
|
.swgroup = TEGRA_SWGROUP_HC,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 22,
|
|
},
|
|
.la = {
|
|
.reg = 0x314,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x10,
|
|
},
|
|
}, {
|
|
.id = 0x37,
|
|
.name = "ispw",
|
|
.swgroup = TEGRA_SWGROUP_ISP,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 23,
|
|
},
|
|
.la = {
|
|
.reg = 0x31c,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x38,
|
|
.name = "mpcorelpw",
|
|
.swgroup = TEGRA_SWGROUP_MPCORELP,
|
|
.la = {
|
|
.reg = 0x324,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0e,
|
|
},
|
|
}, {
|
|
.id = 0x39,
|
|
.name = "mpcorew",
|
|
.swgroup = TEGRA_SWGROUP_MPCORE,
|
|
.la = {
|
|
.reg = 0x320,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x0e,
|
|
},
|
|
}, {
|
|
.id = 0x3a,
|
|
.name = "mpecswr",
|
|
.swgroup = TEGRA_SWGROUP_MPE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 26,
|
|
},
|
|
.la = {
|
|
.reg = 0x330,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x3b,
|
|
.name = "ppcsahbdmaw",
|
|
.swgroup = TEGRA_SWGROUP_PPCS,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 27,
|
|
},
|
|
.la = {
|
|
.reg = 0x348,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x10,
|
|
},
|
|
}, {
|
|
.id = 0x3c,
|
|
.name = "ppcsahbslvw",
|
|
.swgroup = TEGRA_SWGROUP_PPCS,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 28,
|
|
},
|
|
.la = {
|
|
.reg = 0x348,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x06,
|
|
},
|
|
}, {
|
|
.id = 0x3d,
|
|
.name = "sataw",
|
|
.swgroup = TEGRA_SWGROUP_SATA,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 29,
|
|
},
|
|
.la = {
|
|
.reg = 0x350,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x33,
|
|
},
|
|
}, {
|
|
.id = 0x3e,
|
|
.name = "vdebsevw",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 30,
|
|
},
|
|
.la = {
|
|
.reg = 0x35c,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x3f,
|
|
.name = "vdedbgw",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x22c,
|
|
.bit = 31,
|
|
},
|
|
.la = {
|
|
.reg = 0x35c,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0xff,
|
|
},
|
|
}, {
|
|
.id = 0x40,
|
|
.name = "vdembew",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 0,
|
|
},
|
|
.la = {
|
|
.reg = 0x360,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x42,
|
|
},
|
|
}, {
|
|
.id = 0x41,
|
|
.name = "vdetpmw",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 1,
|
|
},
|
|
.la = {
|
|
.reg = 0x360,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x2a,
|
|
},
|
|
},
|
|
};
|
|
|
|
static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
|
|
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
|
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
|
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
|
|
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
|
|
{ .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
|
|
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
|
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
|
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
|
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
|
|
{ .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
|
|
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
|
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
|
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
|
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
|
|
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
|
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
|
|
};
|
|
|
|
static const struct tegra_smmu_soc tegra30_smmu_soc = {
|
|
.clients = tegra30_mc_clients,
|
|
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
|
|
.swgroups = tegra30_swgroups,
|
|
.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
|
|
.supports_round_robin_arbitration = false,
|
|
.supports_request_limit = false,
|
|
.num_tlb_lines = 16,
|
|
.num_asids = 4,
|
|
};
|
|
|
|
const struct tegra_mc_soc tegra30_mc_soc = {
|
|
.clients = tegra30_mc_clients,
|
|
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
|
|
.num_address_bits = 32,
|
|
.atom_size = 16,
|
|
.client_id_mask = 0x7f,
|
|
.smmu = &tegra30_smmu_soc,
|
|
};
|