mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-25 15:31:01 +07:00
b6835ea777
The default value of ARCH_SLAB_MINALIGN in "include/linux/slab.h" is "__alignof__(unsigned long long)" which for ARC unexpectedly turns out to be 4. This is not a compiler bug, but as defined by ARC ABI [1] Thus slab allocator would allocate a struct which is 32-bit aligned, which is generally OK even if struct has long long members. There was however potetial problem when it had any atomic64_t which use LLOCKD/SCONDD instructions which are required by ISA to take 64-bit addresses. This is the problem we ran into [ 4.015732] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null) [ 4.167881] Misaligned Access [ 4.172356] Path: /bin/busybox.nosuid [ 4.176004] CPU: 2 PID: 171 Comm: rm Not tainted 4.19.14-yocto-standard #1 [ 4.182851] [ 4.182851] [ECR ]: 0x000d0000 => Check Programmer's Manual [ 4.190061] [EFA ]: 0xbeaec3fc [ 4.190061] [BLINK ]: ext4_delete_entry+0x210/0x234 [ 4.190061] [ERET ]: ext4_delete_entry+0x13e/0x234 [ 4.202985] [STAT32]: 0x80080002 : IE K [ 4.207236] BTA: 0x9009329c SP: 0xbe5b1ec4 FP: 0x00000000 [ 4.212790] LPS: 0x9074b118 LPE: 0x9074b120 LPC: 0x00000000 [ 4.218348] r00: 0x00000040 r01: 0x00000021 r02: 0x00000001 ... ... [ 4.270510] Stack Trace: [ 4.274510] ext4_delete_entry+0x13e/0x234 [ 4.278695] ext4_rmdir+0xe0/0x238 [ 4.282187] vfs_rmdir+0x50/0xf0 [ 4.285492] do_rmdir+0x9e/0x154 [ 4.288802] EV_Trap+0x110/0x114 The fix is to make sure slab allocations are 64-bit aligned. Do note that atomic64_t is __attribute__((aligned(8)) which means gcc does generate 64-bit aligned references, relative to beginning of container struct. However the issue is if the container itself is not 64-bit aligned, atomic64_t ends up unaligned which is what this patch ensures. [1] https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/wiki/files/ARCv2_ABI.pdf Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: <stable@vger.kernel.org> # 4.8+ Signed-off-by: Vineet Gupta <vgupta@synopsys.com> [vgupta: reworked changelog, added dependency on LL64+LLSC]
134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/*
|
|
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ARC_ASM_CACHE_H
|
|
#define __ARC_ASM_CACHE_H
|
|
|
|
/* In case $$ not config, setup a dummy number for rest of kernel */
|
|
#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
|
|
#define L1_CACHE_SHIFT 6
|
|
#else
|
|
#define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
|
|
#endif
|
|
|
|
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
|
#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
|
|
|
|
/*
|
|
* ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
|
|
* Ideal for wiring memory mapped peripherals as we don't need to do
|
|
* explicit uncached accesses (LD.di/ST.di) hence more portable drivers
|
|
*/
|
|
#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/* Uncached access macros */
|
|
#define arc_read_uncached_32(ptr) \
|
|
({ \
|
|
unsigned int __ret; \
|
|
__asm__ __volatile__( \
|
|
" ld.di %0, [%1] \n" \
|
|
: "=r"(__ret) \
|
|
: "r"(ptr)); \
|
|
__ret; \
|
|
})
|
|
|
|
#define arc_write_uncached_32(ptr, data)\
|
|
({ \
|
|
__asm__ __volatile__( \
|
|
" st.di %0, [%1] \n" \
|
|
: \
|
|
: "r"(data), "r"(ptr)); \
|
|
})
|
|
|
|
/* Largest line length for either L1 or L2 is 128 bytes */
|
|
#define SMP_CACHE_BYTES 128
|
|
#define cache_line_size() SMP_CACHE_BYTES
|
|
#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
|
|
|
|
/*
|
|
* Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
|
|
* ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
|
|
* alignment for any atomic64_t embedded in buffer.
|
|
* Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
|
|
* value of 4 (and not 8) in ARC ABI.
|
|
*/
|
|
#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
|
|
#define ARCH_SLAB_MINALIGN 8
|
|
#endif
|
|
|
|
extern void arc_cache_init(void);
|
|
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
|
|
extern void read_decode_cache_bcr(void);
|
|
|
|
extern int ioc_enable;
|
|
extern unsigned long perip_base, perip_end;
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
/* Instruction cache related Auxiliary registers */
|
|
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
|
|
#define ARC_REG_IC_IVIC 0x10
|
|
#define ARC_REG_IC_CTRL 0x11
|
|
#define ARC_REG_IC_IVIR 0x16
|
|
#define ARC_REG_IC_ENDR 0x17
|
|
#define ARC_REG_IC_IVIL 0x19
|
|
#define ARC_REG_IC_PTAG 0x1E
|
|
#define ARC_REG_IC_PTAG_HI 0x1F
|
|
|
|
/* Bit val in IC_CTRL */
|
|
#define IC_CTRL_DIS 0x1
|
|
|
|
/* Data cache related Auxiliary registers */
|
|
#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
|
|
#define ARC_REG_DC_IVDC 0x47
|
|
#define ARC_REG_DC_CTRL 0x48
|
|
#define ARC_REG_DC_IVDL 0x4A
|
|
#define ARC_REG_DC_FLSH 0x4B
|
|
#define ARC_REG_DC_FLDL 0x4C
|
|
#define ARC_REG_DC_STARTR 0x4D
|
|
#define ARC_REG_DC_ENDR 0x4E
|
|
#define ARC_REG_DC_PTAG 0x5C
|
|
#define ARC_REG_DC_PTAG_HI 0x5F
|
|
|
|
/* Bit val in DC_CTRL */
|
|
#define DC_CTRL_DIS 0x001
|
|
#define DC_CTRL_INV_MODE_FLUSH 0x040
|
|
#define DC_CTRL_FLUSH_STATUS 0x100
|
|
#define DC_CTRL_RGN_OP_INV 0x200
|
|
#define DC_CTRL_RGN_OP_MSK 0x200
|
|
|
|
/*System-level cache (L2 cache) related Auxiliary registers */
|
|
#define ARC_REG_SLC_CFG 0x901
|
|
#define ARC_REG_SLC_CTRL 0x903
|
|
#define ARC_REG_SLC_FLUSH 0x904
|
|
#define ARC_REG_SLC_INVALIDATE 0x905
|
|
#define ARC_AUX_SLC_IVDL 0x910
|
|
#define ARC_AUX_SLC_FLDL 0x912
|
|
#define ARC_REG_SLC_RGN_START 0x914
|
|
#define ARC_REG_SLC_RGN_START1 0x915
|
|
#define ARC_REG_SLC_RGN_END 0x916
|
|
#define ARC_REG_SLC_RGN_END1 0x917
|
|
|
|
/* Bit val in SLC_CONTROL */
|
|
#define SLC_CTRL_DIS 0x001
|
|
#define SLC_CTRL_IM 0x040
|
|
#define SLC_CTRL_BUSY 0x100
|
|
#define SLC_CTRL_RGN_OP_INV 0x200
|
|
|
|
/* IO coherency related Auxiliary registers */
|
|
#define ARC_REG_IO_COH_ENABLE 0x500
|
|
#define ARC_IO_COH_ENABLE_BIT BIT(0)
|
|
#define ARC_REG_IO_COH_PARTIAL 0x501
|
|
#define ARC_IO_COH_PARTIAL_BIT BIT(0)
|
|
#define ARC_REG_IO_COH_AP0_BASE 0x508
|
|
#define ARC_REG_IO_COH_AP0_SIZE 0x509
|
|
|
|
#endif /* _ASM_CACHE_H */
|