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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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57ef579878
The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs. The node is simply added in the meson-gxbb.dtsi file. For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific dtsi files. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: s/MALI/Mali in changelog] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
44 lines
1.4 KiB
Plaintext
44 lines
1.4 KiB
Plaintext
/*
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* Copyright (c) 2017 BayLibre SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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&apb {
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mali: gpu@c0000 {
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compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
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reg = <0x0 0xc0000 0x0 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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/*
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* Mali clocking is provided by two identical clock paths
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* MALI_0 and MALI_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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*/
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assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
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<&clkc CLKID_MALI_0>,
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<&clkc CLKID_MALI>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_MALI_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>; /* Do Nothing */
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};
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};
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