mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 11:46:47 +07:00
a90b858cfe
Upstream commit:
95d76acc75 ("x86, irq: Count legacy IRQs by legacy_pic->nr_legacy_irqs instead of NR_IRQS_LEGACY")
removed reserved interrupts for the platforms that do not have a legacy IOAPIC.
Which breaks the boot on Intel MID platforms such as Medfield:
BUG: unable to handle kernel NULL pointer dereference at 0000003a
IP: [<c107079a>] setup_irq+0xf/0x4d [ 0.000000] *pdpt = 0000000000000000 *pde = 9bbf32453167e510
The culprit is an uncoditional setting of IRQ2 which is used
as cascade IRQ on legacy platforms. It seems we have to check
if we have enough legacy IRQs reserved before we can call
setup_irq().
The fix adds such check in native_init_IRQ() and in setup_default_timer_irq().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jiang Liu <jiang.liu@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: David Cohen <david.a.cohen@linux.intel.com>
Link: http://lkml.kernel.org/r/1405931920-12871-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
213 lines
5.4 KiB
C
213 lines
5.4 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/random.h>
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#include <linux/kprobes.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/atomic.h>
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#include <asm/timer.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/traps.h>
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#include <asm/prom.h>
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.name = "cascade",
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.flags = IRQF_NO_THREAD,
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... NR_VECTORS - 1] = VECTOR_UNDEFINED,
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};
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int vector_used_by_percpu_irq(unsigned int vector)
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{
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int cpu;
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for_each_online_cpu(cpu) {
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if (per_cpu(vector_irq, cpu)[vector] > VECTOR_UNDEFINED)
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return 1;
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}
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return 0;
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}
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void __init init_ISA_irqs(void)
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{
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struct irq_chip *chip = legacy_pic->chip;
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const char *name = chip->name;
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int i;
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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init_bsp_APIC();
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#endif
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legacy_pic->init(0);
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for (i = 0; i < nr_legacy_irqs(); i++)
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irq_set_chip_and_handler_name(i, chip, handle_level_irq, name);
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}
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void __init init_IRQ(void)
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{
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int i;
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/*
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* On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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* then this configuration will likely be static after the boot. If
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* these IRQ's are handled by more mordern controllers like IO-APIC,
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* then this vector space can be freed and re-used dynamically as the
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* irq's migrate etc.
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*/
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for (i = 0; i < nr_legacy_irqs(); i++)
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per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
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x86_init.irqs.intr_init();
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}
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/*
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* Setup the vector to irq mappings.
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*/
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void setup_vector_irq(int cpu)
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{
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#ifndef CONFIG_X86_IO_APIC
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int irq;
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/*
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* On most of the platforms, legacy PIC delivers the interrupts on the
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* boot cpu. But there are certain platforms where PIC interrupts are
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* delivered to multiple cpu's. If the legacy IRQ is handled by the
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* legacy PIC, for the new cpu that is coming online, setup the static
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* legacy vector to irq mapping:
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*/
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for (irq = 0; irq < nr_legacy_irqs(); irq++)
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per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
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#endif
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__setup_vector_irq(cpu);
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}
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static void __init smp_intr_init(void)
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{
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#ifdef CONFIG_SMP
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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/*
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* IPI, driven by wakeup.
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*/
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alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
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/* IPI for generic function call */
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alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
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/* IPI for generic single function call */
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alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
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call_function_single_interrupt);
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/* Low priority IPI to cleanup after moving an irq */
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set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
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/* IPI used for rebooting/stopping */
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alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
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#endif
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#endif /* CONFIG_SMP */
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}
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static void __init apic_intr_init(void)
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{
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smp_intr_init();
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#ifdef CONFIG_X86_THERMAL_VECTOR
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alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
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#endif
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* IPI for X86 platform specific use */
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alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
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#ifdef CONFIG_HAVE_KVM
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/* IPI for KVM to deliver posted interrupt */
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alloc_intr_gate(POSTED_INTR_VECTOR, kvm_posted_intr_ipi);
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#endif
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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/* IRQ work interrupts: */
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# ifdef CONFIG_IRQ_WORK
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alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
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# endif
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#endif
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}
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void __init native_init_IRQ(void)
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{
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int i;
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/* Execute any quirks before the call gates are initialised: */
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x86_init.irqs.pre_vector_init();
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apic_intr_init();
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/*
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* Cover the whole vector space, no vector can escape
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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*/
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i = FIRST_EXTERNAL_VECTOR;
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for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
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/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
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set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
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}
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if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
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setup_irq(2, &irq2);
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#ifdef CONFIG_X86_32
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irq_ctx_init(smp_processor_id());
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#endif
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}
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