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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ba62608110
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
474 lines
12 KiB
C
474 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson-AXG Clock Controller Driver
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*
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* Copyright (c) 2016 Baylibre SAS.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Copyright (c) 2019 Baylibre SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/mfd/syscon.h>
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#include "meson-aoclk.h"
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#include "g12a-aoclk.h"
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#include "clk-regmap.h"
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#include "clk-dualdiv.h"
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/*
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* AO Configuration Clock registers offsets
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* Register offsets from the data sheet must be multiplied by 4.
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*/
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#define AO_RTI_STATUS_REG3 0x0C
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_CLK_GATE0 0x4c
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#define AO_CLK_GATE0_SP 0x50
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#define AO_OSCIN_CNTL 0x58
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#define AO_CEC_CLK_CNTL_REG0 0x74
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#define AO_CEC_CLK_CNTL_REG1 0x78
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#define AO_SAR_CLK 0x90
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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/*
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* Like every other peripheral clock gate in Amlogic Clock drivers,
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* we are using CLK_IGNORE_UNUSED here, so we keep the state of the
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* bootloader. The goal is to remove this flag at some point.
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* Actually removing it will require some extensive test to be done safely.
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*/
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#define AXG_AO_GATE(_name, _reg, _bit) \
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static struct clk_regmap g12a_aoclk_##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "g12a_ao_" #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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}
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AXG_AO_GATE(ahb, AO_CLK_GATE0, 0);
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AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1);
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AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2);
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AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3);
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AXG_AO_GATE(uart, AO_CLK_GATE0, 4);
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AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5);
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AXG_AO_GATE(uart2, AO_CLK_GATE0, 6);
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AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7);
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AXG_AO_GATE(saradc, AO_CLK_GATE0, 8);
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AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0);
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AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1);
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AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2);
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AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3);
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AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4);
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AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5);
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static struct clk_regmap g12a_aoclk_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTI_PWR_CNTL_REG0,
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.bit_idx = 14,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cts_oscin",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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static const struct meson_clk_dualdiv_param g12a_32k_div_table[] = {
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{
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.dual = 1,
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.n1 = 733,
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.m1 = 8,
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.n2 = 732,
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.m2 = 11,
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}, {}
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};
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/* 32k_by_oscin clock */
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static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_cts_oscin.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 28,
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.width = 1,
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},
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.table = g12a_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_32k_by_oscin_pre.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTC_ALT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_32k_by_oscin_div.hw,
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&g12a_aoclk_32k_by_oscin_pre.hw,
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_32k_by_oscin_sel.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* cec clock */
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static struct clk_regmap g12a_aoclk_cec_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_CEC_CLK_CNTL_REG0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_cts_oscin.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_cec_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_CEC_CLK_CNTL_REG1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_CEC_CLK_CNTL_REG1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 28,
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.width = 1,
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},
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.table = g12a_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_cec_pre.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_cec_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CEC_CLK_CNTL_REG1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_cec_div.hw,
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&g12a_aoclk_cec_pre.hw,
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_cec = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_CEC_CLK_CNTL_REG0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_cec_sel.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 10,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cts_rtc_oscin",
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.ops = &clk_regmap_mux_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .hw = &g12a_aoclk_32k_by_oscin.hw },
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{ .fw_name = "ext-32k-0", },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_clk81 = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 8,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_clk81",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "mpeg-clk", },
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{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_SAR_CLK,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "xtal", },
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{ .hw = &g12a_aoclk_clk81.hw },
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},
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.num_parents = 2,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_SAR_CLK,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_saradc_mux.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_gate = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_SAR_CLK,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_gate",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_aoclk_saradc_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const unsigned int g12a_aoclk_reset[] = {
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[RESET_AO_IR_IN] = 16,
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[RESET_AO_UART] = 17,
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[RESET_AO_I2C_M] = 18,
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[RESET_AO_I2C_S] = 19,
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[RESET_AO_SAR_ADC] = 20,
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[RESET_AO_UART2] = 22,
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[RESET_AO_IR_OUT] = 23,
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};
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static struct clk_regmap *g12a_aoclk_regmap[] = {
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&g12a_aoclk_ahb,
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&g12a_aoclk_ir_in,
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&g12a_aoclk_i2c_m0,
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&g12a_aoclk_i2c_s0,
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&g12a_aoclk_uart,
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&g12a_aoclk_prod_i2c,
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&g12a_aoclk_uart2,
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&g12a_aoclk_ir_out,
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&g12a_aoclk_saradc,
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&g12a_aoclk_mailbox,
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&g12a_aoclk_m3,
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&g12a_aoclk_ahb_sram,
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&g12a_aoclk_rti,
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&g12a_aoclk_m4_fclk,
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&g12a_aoclk_m4_hclk,
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&g12a_aoclk_cts_oscin,
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&g12a_aoclk_32k_by_oscin_pre,
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&g12a_aoclk_32k_by_oscin_div,
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&g12a_aoclk_32k_by_oscin_sel,
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&g12a_aoclk_32k_by_oscin,
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&g12a_aoclk_cec_pre,
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&g12a_aoclk_cec_div,
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&g12a_aoclk_cec_sel,
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&g12a_aoclk_cec,
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&g12a_aoclk_cts_rtc_oscin,
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&g12a_aoclk_clk81,
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&g12a_aoclk_saradc_mux,
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&g12a_aoclk_saradc_div,
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&g12a_aoclk_saradc_gate,
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};
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static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
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.hws = {
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[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
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[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
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[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
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[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
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[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
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[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
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[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
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[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
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[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
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[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
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[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
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[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
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[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
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[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
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|
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
|
|
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
|
|
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
|
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[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
|
|
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
|
|
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
|
|
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
|
|
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
|
|
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
|
|
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
|
|
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
|
|
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
|
|
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
|
|
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
|
|
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
|
|
},
|
|
.num = NR_CLKS,
|
|
};
|
|
|
|
static const struct meson_aoclk_data g12a_aoclkc_data = {
|
|
.reset_reg = AO_RTI_GEN_CNTL_REG0,
|
|
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
|
|
.reset = g12a_aoclk_reset,
|
|
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
|
|
.clks = g12a_aoclk_regmap,
|
|
.hw_data = &g12a_aoclk_onecell_data,
|
|
};
|
|
|
|
static const struct of_device_id g12a_aoclkc_match_table[] = {
|
|
{
|
|
.compatible = "amlogic,meson-g12a-aoclkc",
|
|
.data = &g12a_aoclkc_data,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver g12a_aoclkc_driver = {
|
|
.probe = meson_aoclkc_probe,
|
|
.driver = {
|
|
.name = "g12a-aoclkc",
|
|
.of_match_table = g12a_aoclkc_match_table,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver(g12a_aoclkc_driver);
|