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f0cd9ae5d0
Pick up dependent changes.
544 lines
15 KiB
C
544 lines
15 KiB
C
/*
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* This file contains driver for the Cadence Triple Timer Counter Rev 06
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*
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* Copyright (C) 2011-2013 Xilinx
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*
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* based on arch/mips/kernel/time.c timer driver
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/sched_clock.h>
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/*
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* This driver configures the 2 16/32-bit count-up timers as follows:
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*
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* T1: Timer 1, clocksource for generic timekeeping
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* T2: Timer 2, clockevent source for hrtimers
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* T3: Timer 3, <unused>
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*
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* The input frequency to the timer module for emulation is 2.5MHz which is
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* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
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* the timers are clocked at 78.125KHz (12.8 us resolution).
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* The input frequency to the timer module in silicon is configurable and
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* obtained from device tree. The pre-scaler of 32 is used.
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*/
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/*
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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*/
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#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
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#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
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#define TTC_CLK_CNTRL_PSV_MASK 0x1e
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#define TTC_CLK_CNTRL_PSV_SHIFT 1
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/*
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* Setup the timers to use pre-scaling, using a fixed value for now that will
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* work across most input frequency, but it may need to be more dynamic
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*/
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#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
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#define PRESCALE 2048 /* The exponent must match this */
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#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
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#define CLK_CNTRL_PRESCALE_EN 1
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#define CNT_CNTRL_RESET (1 << 4)
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#define MAX_F_ERR 50
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/**
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* struct ttc_timer - This definition defines local timer structure
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*
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* @base_addr: Base address of timer
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* @freq: Timer input clock frequency
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* @clk: Associated clock source
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* @clk_rate_change_nb Notifier block for clock rate changes
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*/
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struct ttc_timer {
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void __iomem *base_addr;
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unsigned long freq;
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struct clk *clk;
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struct notifier_block clk_rate_change_nb;
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};
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#define to_ttc_timer(x) \
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container_of(x, struct ttc_timer, clk_rate_change_nb)
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struct ttc_timer_clocksource {
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u32 scale_clk_ctrl_reg_old;
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u32 scale_clk_ctrl_reg_new;
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struct ttc_timer ttc;
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struct clocksource cs;
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};
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#define to_ttc_timer_clksrc(x) \
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container_of(x, struct ttc_timer_clocksource, cs)
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struct ttc_timer_clockevent {
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struct ttc_timer ttc;
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struct clock_event_device ce;
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};
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#define to_ttc_timer_clkevent(x) \
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container_of(x, struct ttc_timer_clockevent, ce)
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static void __iomem *ttc_sched_clock_val_reg;
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/**
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* ttc_set_interval - Set the timer interval value
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*
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* @timer: Pointer to the timer instance
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* @cycles: Timer interval ticks
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**/
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static void ttc_set_interval(struct ttc_timer *timer,
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unsigned long cycles)
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{
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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/*
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* Reset the counter (0x10) so that it starts from 0, one-shot
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* mode makes this needed for timing to be right.
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*/
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ctrl_reg |= CNT_CNTRL_RESET;
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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}
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/**
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* ttc_clock_event_interrupt - Clock event timer interrupt handler
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*
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* @irq: IRQ number of the Timer
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* @dev_id: void pointer to the ttc_timer instance
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*
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* returns: Always IRQ_HANDLED - success
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**/
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static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
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{
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struct ttc_timer_clockevent *ttce = dev_id;
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struct ttc_timer *timer = &ttce->ttc;
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/* Acknowledge the interrupt and call event handler */
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readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
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ttce->ce.event_handler(&ttce->ce);
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return IRQ_HANDLED;
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}
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/**
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* __ttc_clocksource_read - Reads the timer counter register
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*
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* returns: Current timer counter register value
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**/
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static u64 __ttc_clocksource_read(struct clocksource *cs)
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{
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struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
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return (u64)readl_relaxed(timer->base_addr +
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TTC_COUNT_VAL_OFFSET);
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}
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static u64 notrace ttc_sched_clock_read(void)
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{
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return readl_relaxed(ttc_sched_clock_val_reg);
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}
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/**
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* ttc_set_next_event - Sets the time interval for next event
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*
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* @cycles: Timer interval ticks
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* @evt: Address of clock event instance
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*
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* returns: Always 0 - success
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**/
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static int ttc_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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ttc_set_interval(timer, cycles);
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return 0;
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}
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/**
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* ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
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*
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* @evt: Address of clock event instance
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**/
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static int ttc_shutdown(struct clock_event_device *evt)
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{
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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u32 ctrl_reg;
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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return 0;
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}
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static int ttc_set_periodic(struct clock_event_device *evt)
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{
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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ttc_set_interval(timer,
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DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
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return 0;
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}
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static int ttc_resume(struct clock_event_device *evt)
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{
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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u32 ctrl_reg;
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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return 0;
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}
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static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct ttc_timer *ttc = to_ttc_timer(nb);
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struct ttc_timer_clocksource *ttccs = container_of(ttc,
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struct ttc_timer_clocksource, ttc);
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switch (event) {
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case PRE_RATE_CHANGE:
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{
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u32 psv;
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unsigned long factor, rate_low, rate_high;
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if (ndata->new_rate > ndata->old_rate) {
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factor = DIV_ROUND_CLOSEST(ndata->new_rate,
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ndata->old_rate);
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rate_low = ndata->old_rate;
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rate_high = ndata->new_rate;
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} else {
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factor = DIV_ROUND_CLOSEST(ndata->old_rate,
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ndata->new_rate);
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rate_low = ndata->new_rate;
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rate_high = ndata->old_rate;
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}
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if (!is_power_of_2(factor))
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return NOTIFY_BAD;
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if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
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return NOTIFY_BAD;
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factor = __ilog2_u32(factor);
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/*
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* store timer clock ctrl register so we can restore it in case
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* of an abort.
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*/
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ttccs->scale_clk_ctrl_reg_old =
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readl_relaxed(ttccs->ttc.base_addr +
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TTC_CLK_CNTRL_OFFSET);
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psv = (ttccs->scale_clk_ctrl_reg_old &
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TTC_CLK_CNTRL_PSV_MASK) >>
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TTC_CLK_CNTRL_PSV_SHIFT;
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if (ndata->new_rate < ndata->old_rate)
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psv -= factor;
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else
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psv += factor;
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/* prescaler within legal range? */
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if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
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return NOTIFY_BAD;
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ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
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~TTC_CLK_CNTRL_PSV_MASK;
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ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
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/* scale down: adjust divider in post-change notification */
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if (ndata->new_rate < ndata->old_rate)
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return NOTIFY_DONE;
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/* scale up: adjust divider now - before frequency change */
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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}
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case POST_RATE_CHANGE:
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/* scale up: pre-change notification did the adjustment */
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if (ndata->new_rate > ndata->old_rate)
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return NOTIFY_OK;
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/* scale down: adjust divider now - after frequency change */
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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case ABORT_RATE_CHANGE:
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/* we have to undo the adjustment in case we scale up */
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if (ndata->new_rate < ndata->old_rate)
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return NOTIFY_OK;
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/* restore original register value */
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writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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/* fall through */
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default:
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return NOTIFY_DONE;
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}
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return NOTIFY_DONE;
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}
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static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
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u32 timer_width)
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{
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struct ttc_timer_clocksource *ttccs;
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int err;
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ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
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if (!ttccs)
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return -ENOMEM;
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ttccs->ttc.clk = clk;
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err = clk_prepare_enable(ttccs->ttc.clk);
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if (err) {
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kfree(ttccs);
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return err;
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}
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ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
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ttccs->ttc.clk_rate_change_nb.notifier_call =
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ttc_rate_change_clocksource_cb;
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ttccs->ttc.clk_rate_change_nb.next = NULL;
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err = clk_notifier_register(ttccs->ttc.clk,
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&ttccs->ttc.clk_rate_change_nb);
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if (err)
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pr_warn("Unable to register clock notifier.\n");
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ttccs->ttc.base_addr = base;
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ttccs->cs.name = "ttc_clocksource";
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ttccs->cs.rating = 200;
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ttccs->cs.read = __ttc_clocksource_read;
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ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
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ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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/*
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* Setup the clock source counter to be an incrementing counter
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
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* it by 32 also. Let it start running now.
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*/
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writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(CNT_CNTRL_RESET,
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ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
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if (err) {
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kfree(ttccs);
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return err;
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}
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ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
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sched_clock_register(ttc_sched_clock_read, timer_width,
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ttccs->ttc.freq / PRESCALE);
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return 0;
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}
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static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct ttc_timer *ttc = to_ttc_timer(nb);
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struct ttc_timer_clockevent *ttcce = container_of(ttc,
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struct ttc_timer_clockevent, ttc);
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switch (event) {
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case POST_RATE_CHANGE:
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/* update cached frequency */
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ttc->freq = ndata->new_rate;
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clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
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/* fall through */
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case PRE_RATE_CHANGE:
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case ABORT_RATE_CHANGE:
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default:
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return NOTIFY_DONE;
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}
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}
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static int __init ttc_setup_clockevent(struct clk *clk,
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void __iomem *base, u32 irq)
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{
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struct ttc_timer_clockevent *ttcce;
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int err;
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ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
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if (!ttcce)
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return -ENOMEM;
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ttcce->ttc.clk = clk;
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err = clk_prepare_enable(ttcce->ttc.clk);
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if (err) {
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kfree(ttcce);
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return err;
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}
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ttcce->ttc.clk_rate_change_nb.notifier_call =
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ttc_rate_change_clockevent_cb;
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ttcce->ttc.clk_rate_change_nb.next = NULL;
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err = clk_notifier_register(ttcce->ttc.clk,
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&ttcce->ttc.clk_rate_change_nb);
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if (err) {
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pr_warn("Unable to register clock notifier.\n");
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return err;
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}
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ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
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ttcce->ttc.base_addr = base;
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ttcce->ce.name = "ttc_clockevent";
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ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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ttcce->ce.set_next_event = ttc_set_next_event;
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ttcce->ce.set_state_shutdown = ttc_shutdown;
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ttcce->ce.set_state_periodic = ttc_set_periodic;
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ttcce->ce.set_state_oneshot = ttc_shutdown;
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ttcce->ce.tick_resume = ttc_resume;
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ttcce->ce.rating = 200;
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ttcce->ce.irq = irq;
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ttcce->ce.cpumask = cpu_possible_mask;
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/*
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* Setup the clock event timer to be an interval timer which
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* is prescaled by 32 using the interval interrupt. Leave it
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* disabled for now.
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*/
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writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
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err = request_irq(irq, ttc_clock_event_interrupt,
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IRQF_TIMER, ttcce->ce.name, ttcce);
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if (err) {
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kfree(ttcce);
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return err;
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}
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clockevents_config_and_register(&ttcce->ce,
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ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
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|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ttc_timer_init - Initialize the timer
|
|
*
|
|
* Initializes the timer hardware and register the clock source and clock event
|
|
* timers with Linux kernal timer framework
|
|
*/
|
|
static int __init ttc_timer_init(struct device_node *timer)
|
|
{
|
|
unsigned int irq;
|
|
void __iomem *timer_baseaddr;
|
|
struct clk *clk_cs, *clk_ce;
|
|
static int initialized;
|
|
int clksel, ret;
|
|
u32 timer_width = 16;
|
|
|
|
if (initialized)
|
|
return 0;
|
|
|
|
initialized = 1;
|
|
|
|
/*
|
|
* Get the 1st Triple Timer Counter (TTC) block from the device tree
|
|
* and use it. Note that the event timer uses the interrupt and it's the
|
|
* 2nd TTC hence the irq_of_parse_and_map(,1)
|
|
*/
|
|
timer_baseaddr = of_iomap(timer, 0);
|
|
if (!timer_baseaddr) {
|
|
pr_err("ERROR: invalid timer base address\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq = irq_of_parse_and_map(timer, 1);
|
|
if (irq <= 0) {
|
|
pr_err("ERROR: invalid interrupt number\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
of_property_read_u32(timer, "timer-width", &timer_width);
|
|
|
|
clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
|
|
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
|
|
clk_cs = of_clk_get(timer, clksel);
|
|
if (IS_ERR(clk_cs)) {
|
|
pr_err("ERROR: timer input clock not found\n");
|
|
return PTR_ERR(clk_cs);
|
|
}
|
|
|
|
clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
|
|
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
|
|
clk_ce = of_clk_get(timer, clksel);
|
|
if (IS_ERR(clk_ce)) {
|
|
pr_err("ERROR: timer input clock not found\n");
|
|
return PTR_ERR(clk_ce);
|
|
}
|
|
|
|
ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
|