Will Deacon 679db70801 arm64: entry: Place an SB sequence following an ERET instruction ... Some CPUs can speculate past an ERET instruction and potentially perform speculative accesses to memory before processing the exception return. Since the register state is often controlled by a lower privilege level at the point of an ERET, this could potentially be used as part of a side-channel attack. This patch emits an SB sequence after each ERET so that speculation is held up on exception return. Signed-off-by: Will Deacon <will.deacon@arm.com>		2018-12-06 16:47:05 +00:00
..
hyp	arm64: entry: Place an SB sequence following an ERET instruction	2018-12-06 16:47:05 +00:00
debug.c
fpsimd.c
guest.c	KVM updates for v4.20	2018-10-25 17:57:35 -07:00
handle_exit.c	KVM: arm64: Safety check PSTATE when entering guest and handle IL	2018-10-19 11:13:03 +01:00
hyp-init.S	arm64: KVM: Enable Common Not Private translations	2018-09-18 12:03:34 +01:00
hyp.S
inject_fault.c	arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS	2018-07-21 16:02:30 +01:00
irq.h
Kconfig
Makefile
regmap.c	kvm/arm: use PSR_AA32 definitions	2018-07-05 17:24:15 +01:00
reset.c	arm/arm64: KVM: Enable 32 bits kvm vcpu events support	2018-10-18 10:14:03 +01:00
sys_regs_generic_v8.c
sys_regs.c	KVM: arm64: vgic-v3: Add support for ICC_SGI0R_EL1 and ICC_ASGI1R_EL1 accesses	2018-08-12 12:06:35 +01:00
sys_regs.h
trace.h
va_layout.c
vgic-sys-reg-v3.c