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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1db823ee9f
The glue around the core designware IP is significantly different between the Exynos and i.MX implementation, which is reflected in the DT bindings. This changes the i.MX6 binding to reuse as much as possible from the common designware binding and removes old cruft. I removed the optional GPIOs with the following reasoning: - disable-gpio: endpoint specific GPIO, not currently wired up in any code. Should be handled by the PCI device driver, not the host controller driver. - wake-up-gpio: same as above. - power-on-gpio: No user in any upstream DT. This should be handled by a regulator which shouldn't be controlled by the host driver, but rather by the PCI device driver. [bhelgaas: whitespace fixes] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
66 lines
2.0 KiB
Plaintext
66 lines
2.0 KiB
Plaintext
* Samsung Exynos 5440 PCIe interface
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "samsung,exynos5440-pcie"
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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- interrupts: A list of interrupt outputs for level interrupt,
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pulse interrupt, special interrupt.
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Example:
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SoC specific DT Entry:
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
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clocks = <&clock 28>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <4>;
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};
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pcie@2a0000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
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clocks = <&clock 29>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <4>;
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};
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Board specific DT Entry:
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pcie@290000 {
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reset-gpio = <&pin_ctrl 5 0>;
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};
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pcie@2a0000 {
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reset-gpio = <&pin_ctrl 22 0>;
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};
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