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f9626104a5
It is possible to enable CONFIG_MTRR and CONFIG_X86_PAT and end
up with a system with MTRR functionality disabled but PAT
functionality enabled. This can happen, for instance, when the
Xen hypervisor is used where MTRRs are not supported but PAT is.
This can happen on Linux as of commit
47591df505 ("xen: Support Xen pv-domains using PAT")
by Juergen, introduced in v3.19.
Technically, we should assume the proper CPU bits would be set
to disable MTRRs but we can't always rely on this. At least on
the Xen Hypervisor, for instance, only X86_FEATURE_MTRR was
disabled as of Xen 4.4 through Xen commit 586ab6a [0], but not
X86_FEATURE_K6_MTRR, X86_FEATURE_CENTAUR_MCR, or
X86_FEATURE_CYRIX_ARR for instance.
Roger Pau Monné has clarified though that although this is
technically true we will never support PVH on these CPU types so
Xen has no need to disable these bits on those systems. As per
Roger, AMD K6, Centaur and VIA chips don't have the necessary
hardware extensions to allow running PVH guests [1].
As per Toshi it is also possible for the BIOS to disable MTRR
support, in such cases get_mtrr_state() would update the MTRR
state as per the BIOS, we need to propagate this information as
well.
x86 MTRR code relies on quite a bit of checks for mtrr_if being
set to check to see if MTRRs did get set up. Instead, lets
provide a generic getter for that. This also adds a few checks
where they were not before which could potentially safeguard
ourselves against incorrect usage of MTRR where this was not
desirable.
Where possible match error codes as if MTRRs were disabled on
arch/x86/include/asm/mtrr.h.
Lastly, since disabling MTRRs can happen at run time and we
could end up with PAT enabled, best record now in our logs when
MTRRs are disabled.
[0] ~/devel/xen (git::stable-4.5)$ git describe --contains 586ab6a 4.4.0-rc1~18
[1] http://lists.xenproject.org/archives/html/xen-devel/2015-03/msg03460.html
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Antonino Daplas <adaplas@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Davidlohr Bueso <dbueso@suse.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Roger Pau Monné <roger.pau@citrix.com>
Cc: Stefan Bader <stefan.bader@canonical.com>
Cc: Suresh Siddha <sbsiddha@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Toshi Kani <toshi.kani@hp.com>
Cc: Ville Syrjälä <syrjala@sci.fi>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: bhelgaas@google.com
Cc: david.vrabel@citrix.com
Cc: jbeulich@suse.com
Cc: konrad.wilk@oracle.com
Cc: venkatesh.pallipadi@intel.com
Cc: ville.syrjala@linux.intel.com
Cc: xen-devel@lists.xensource.com
Link: http://lkml.kernel.org/r/1426893517-2511-3-git-send-email-mcgrof@do-not-panic.com
Link: http://lkml.kernel.org/r/1432628901-18044-12-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/*
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* local MTRR defines.
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*/
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#include <linux/types.h>
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#include <linux/stddef.h>
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#define MTRR_CHANGE_MASK_FIXED 0x01
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#define MTRR_CHANGE_MASK_VARIABLE 0x02
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#define MTRR_CHANGE_MASK_DEFTYPE 0x04
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extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
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struct mtrr_ops {
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u32 vendor;
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u32 use_intel_if;
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void (*set)(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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void (*set_all)(void);
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void (*get)(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type *type);
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int (*get_free_region)(unsigned long base, unsigned long size,
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int replace_reg);
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int (*validate_add_page)(unsigned long base, unsigned long size,
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unsigned int type);
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int (*have_wrcomb)(void);
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};
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extern int generic_get_free_region(unsigned long base, unsigned long size,
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int replace_reg);
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extern int generic_validate_add_page(unsigned long base, unsigned long size,
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unsigned int type);
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extern const struct mtrr_ops generic_mtrr_ops;
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extern int positive_have_wrcomb(void);
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/* library functions for processor-specific routines */
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struct set_mtrr_context {
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unsigned long flags;
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unsigned long cr4val;
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u32 deftype_lo;
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u32 deftype_hi;
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u32 ccr3;
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};
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void set_mtrr_done(struct set_mtrr_context *ctxt);
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
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void fill_mtrr_var_range(unsigned int index,
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u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
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bool get_mtrr_state(void);
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extern void set_mtrr_ops(const struct mtrr_ops *ops);
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extern u64 size_or_mask, size_and_mask;
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extern const struct mtrr_ops *mtrr_if;
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#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
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#define use_intel() (mtrr_if && mtrr_if->use_intel_if == 1)
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extern unsigned int num_var_ranges;
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extern u64 mtrr_tom2;
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extern struct mtrr_state_type mtrr_state;
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void mtrr_state_warn(void);
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const char *mtrr_attrib_to_str(int x);
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void mtrr_wrmsr(unsigned, unsigned, unsigned);
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/* CPU specific mtrr init functions */
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int amd_init_mtrr(void);
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int cyrix_init_mtrr(void);
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int centaur_init_mtrr(void);
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extern int changed_by_mtrr_cleanup;
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extern int mtrr_cleanup(unsigned address_bits);
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