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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e307cc8941
Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
256 lines
6.0 KiB
C
256 lines
6.0 KiB
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* Copyright (C) 2010,2013, NVIDIA Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/syscore_ops.h>
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#include "board.h"
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#include "iomap.h"
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#define ICTLR_CPU_IEP_VFIQ 0x08
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#define ICTLR_CPU_IEP_FIR 0x14
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#define ICTLR_CPU_IEP_FIR_SET 0x18
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#define ICTLR_CPU_IEP_FIR_CLR 0x1c
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#define ICTLR_CPU_IER 0x20
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#define ICTLR_CPU_IER_SET 0x24
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#define ICTLR_CPU_IER_CLR 0x28
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#define ICTLR_CPU_IEP_CLASS 0x2C
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#define ICTLR_COP_IER 0x30
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#define ICTLR_COP_IER_SET 0x34
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#define ICTLR_COP_IER_CLR 0x38
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#define ICTLR_COP_IEP_CLASS 0x3c
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#define FIRST_LEGACY_IRQ 32
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#define TEGRA_MAX_NUM_ICTLRS 5
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#define SGI_MASK 0xFFFF
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static int num_ictlrs;
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static void __iomem *ictlr_reg_base[] = {
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IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
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};
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#ifdef CONFIG_PM_SLEEP
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static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
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static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
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static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
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static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
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static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
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#endif
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bool tegra_pending_sgi(void)
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{
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u32 pending_set;
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void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
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pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
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if (pending_set & SGI_MASK)
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return true;
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return false;
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}
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static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
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{
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void __iomem *base;
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u32 mask;
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BUG_ON(irq < FIRST_LEGACY_IRQ ||
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irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);
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base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
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mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
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__raw_writel(mask, base + reg);
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}
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static void tegra_mask(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
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}
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static void tegra_unmask(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
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}
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static void tegra_ack(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
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}
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static void tegra_eoi(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
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}
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static int tegra_retrigger(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return 0;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
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return 1;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_set_wake(struct irq_data *d, unsigned int enable)
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{
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u32 irq = d->irq;
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u32 index, mask;
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if (irq < FIRST_LEGACY_IRQ ||
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irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
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return -EINVAL;
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index = ((irq - FIRST_LEGACY_IRQ) / 32);
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mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
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if (enable)
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ictlr_wake_mask[index] |= mask;
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else
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ictlr_wake_mask[index] &= ~mask;
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return 0;
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}
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static int tegra_legacy_irq_suspend(void)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < num_ictlrs; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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/* Save interrupt state */
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cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
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cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
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cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
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cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
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/* Disable COP interrupts */
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writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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/* Disable CPU interrupts */
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writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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/* Enable the wakeup sources of ictlr */
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writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
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}
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local_irq_restore(flags);
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return 0;
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}
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static void tegra_legacy_irq_resume(void)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < num_ictlrs; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
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writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
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writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
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writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
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}
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local_irq_restore(flags);
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}
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static struct syscore_ops tegra_legacy_irq_syscore_ops = {
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.suspend = tegra_legacy_irq_suspend,
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.resume = tegra_legacy_irq_resume,
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};
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int tegra_legacy_irq_syscore_init(void)
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{
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register_syscore_ops(&tegra_legacy_irq_syscore_ops);
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return 0;
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}
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#else
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#define tegra_set_wake NULL
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#endif
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void __init tegra_init_irq(void)
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{
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int i;
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void __iomem *distbase;
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distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
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num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
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if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
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WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
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num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
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num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
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}
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for (i = 0; i < num_ictlrs; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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writel(~0, ictlr + ICTLR_CPU_IER_CLR);
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writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
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}
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gic_arch_extn.irq_ack = tegra_ack;
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gic_arch_extn.irq_eoi = tegra_eoi;
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gic_arch_extn.irq_mask = tegra_mask;
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gic_arch_extn.irq_unmask = tegra_unmask;
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gic_arch_extn.irq_retrigger = tegra_retrigger;
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gic_arch_extn.irq_set_wake = tegra_set_wake;
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gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
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/*
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* Check if there is a devicetree present, since the GIC will be
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* initialized elsewhere under DT.
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*/
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if (!of_have_populated_dt())
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gic_init(0, 29, distbase,
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IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
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}
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