mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 02:55:42 +07:00
25d6463e48
On many MIPS systems the endianness of IP blocks is kept the same as that of the CPU by the hardware. This includes the system controllers on these systems which are controlled via syscon which uses the regmap API which used readl() and writel() to interact with the hardware, meaning that all writes are converted to little endian when writing to the hardware. This caused a bad interaction with the regmap core in big endian mode since it was not aware of the byte swapping and so ended up performing little endian writes. Unfortunately when this issue was noticed it was addressed by updating the DT for the affected devices to specify them as little endian. This happened to work since it resulted in two endianness swaps which cancelled each other out and gave little endian behaviour but meant that the DT was clearly not accurately describing the hardware. The intention of commit29bb45f25f(regmap-mmio: Use native endianness for read/write) was to fix this by making regmap default to native endianness but this breaks most other MMIO users where the hardware has a fixed endianness and the implementation uses the __raw accessors which are not intended to be used outside of architecture code. Instead use the newly added native-endian DT property to say exactly what we want for these systems. Fixes:29bb45f25f(regmap-mmio: Use native endianness for read/write) Reported-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org>
361 lines
7.8 KiB
Plaintext
361 lines
7.8 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm7346";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <163125000>;
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cpu@0 {
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compatible = "brcm,bmips5000";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,bmips5000";
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device_type = "cpu";
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reg = <1>;
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};
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};
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aliases {
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uart0 = &uart0;
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uart1 = &uart1;
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uart2 = &uart2;
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};
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cpu_intc: cpu_intc {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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clocks {
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uart_clk: uart_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <81000000>;
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};
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};
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x10000000 0x01000000>;
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periph_intc: periph_intc@411400 {
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compatible = "brcm,bcm7038-l1-intc";
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reg = <0x411400 0x30>, <0x411600 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>, <3>;
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};
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sun_l2_intc: sun_l2_intc@403000 {
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compatible = "brcm,l2-intc";
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reg = <0x403000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <51>;
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};
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gisb-arb@400000 {
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compatible = "brcm,bcm7400-gisb-arb";
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reg = <0x400000 0xdc>;
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native-endian;
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interrupt-parent = <&sun_l2_intc>;
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interrupts = <0>, <2>;
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brcm,gisb-arb-master-mask = <0x673>;
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brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
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"rdc_0", "raaga_0",
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"jtag_0", "svd_0";
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};
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upg_irq0_intc: upg_irq0_intc@406780 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406780 0x8>;
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brcm,int-map-mask = <0x44>, <0xf000000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <59>, <57>;
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interrupt-names = "upg_main", "upg_bsc";
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};
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upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x408b80 0x8>;
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brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
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brcm,int-fwd-mask = <0>;
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brcm,irq-can-wake;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <60>, <58>, <62>;
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interrupt-names = "upg_main_aon", "upg_bsc_aon",
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"upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
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reg = <0x404000 0x51c>;
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native-endian;
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};
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reboot {
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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uart0: serial@406900 {
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compatible = "ns16550a";
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reg = <0x406900 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <64>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@406940 {
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compatible = "ns16550a";
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reg = <0x406940 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <65>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@406980 {
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compatible = "ns16550a";
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reg = <0x406980 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <66>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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bsca: i2c@406200 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406200 0x58>;
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interrupts = <24>;
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interrupt-names = "upg_bsca";
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status = "disabled";
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};
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bscb: i2c@406280 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406280 0x58>;
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interrupts = <25>;
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interrupt-names = "upg_bscb";
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status = "disabled";
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};
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bscc: i2c@406300 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406300 0x58>;
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interrupts = <26>;
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interrupt-names = "upg_bscc";
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status = "disabled";
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};
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bscd: i2c@406380 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406380 0x58>;
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interrupts = <27>;
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interrupt-names = "upg_bscd";
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status = "disabled";
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};
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bsce: i2c@408980 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_aon_irq0_intc>;
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reg = <0x408980 0x58>;
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interrupts = <27>;
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interrupt-names = "upg_bsce";
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status = "disabled";
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};
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enet0: ethernet@430000 {
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phy-mode = "internal";
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phy-handle = <&phy1>;
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mac-address = [ 00 10 18 36 23 1a ];
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compatible = "brcm,genet-v2";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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reg = <0x430000 0x4c8c>;
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interrupts = <24>, <25>;
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interrupt-parent = <&periph_intc>;
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status = "disabled";
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mdio@e14 {
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compatible = "brcm,genet-mdio-v2";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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reg = <0xe14 0x8>;
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phy1: ethernet-phy@1 {
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max-speed = <100>;
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reg = <0x1>;
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compatible = "brcm,40nm-ephy",
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"ethernet-phy-ieee802.3-c22";
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};
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};
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};
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ehci0: usb@480300 {
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compatible = "brcm,bcm7346-ehci", "generic-ehci";
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reg = <0x480300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <68>;
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status = "disabled";
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};
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ohci0: usb@480400 {
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compatible = "brcm,bcm7346-ohci", "generic-ohci";
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reg = <0x480400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <70>;
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status = "disabled";
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};
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ehci1: usb@480500 {
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compatible = "brcm,bcm7346-ehci", "generic-ehci";
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reg = <0x480500 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <69>;
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status = "disabled";
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};
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ohci1: usb@480600 {
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compatible = "brcm,bcm7346-ohci", "generic-ohci";
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reg = <0x480600 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <71>;
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status = "disabled";
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};
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ehci2: usb@490300 {
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compatible = "brcm,bcm7346-ehci", "generic-ehci";
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reg = <0x490300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <73>;
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status = "disabled";
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};
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ohci2: usb@490400 {
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compatible = "brcm,bcm7346-ohci", "generic-ohci";
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reg = <0x490400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <75>;
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status = "disabled";
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};
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ehci3: usb@490500 {
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compatible = "brcm,bcm7346-ehci", "generic-ehci";
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reg = <0x490500 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <74>;
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status = "disabled";
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};
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ohci3: usb@490600 {
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compatible = "brcm,bcm7346-ohci", "generic-ohci";
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reg = <0x490600 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <76>;
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status = "disabled";
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};
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sata: sata@181000 {
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compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
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reg-names = "ahci", "top-ctrl";
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reg = <0x181000 0xa9c>, <0x180020 0x1c>;
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interrupt-parent = <&periph_intc>;
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interrupts = <40>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,broken-ncq;
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brcm,broken-phy;
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status = "disabled";
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sata0: sata-port@0 {
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reg = <0>;
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phys = <&sata_phy0>;
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};
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sata1: sata-port@1 {
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reg = <1>;
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phys = <&sata_phy1>;
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};
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};
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sata_phy: sata-phy@1800000 {
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compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
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reg = <0x180100 0x0eff>;
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reg-names = "phy";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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sata_phy0: sata-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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sata_phy1: sata-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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};
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};
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