mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 02:55:42 +07:00
25d6463e48
On many MIPS systems the endianness of IP blocks is kept the same as that of the CPU by the hardware. This includes the system controllers on these systems which are controlled via syscon which uses the regmap API which used readl() and writel() to interact with the hardware, meaning that all writes are converted to little endian when writing to the hardware. This caused a bad interaction with the regmap core in big endian mode since it was not aware of the byte swapping and so ended up performing little endian writes. Unfortunately when this issue was noticed it was addressed by updating the DT for the affected devices to specify them as little endian. This happened to work since it resulted in two endianness swaps which cancelled each other out and gave little endian behaviour but meant that the DT was clearly not accurately describing the hardware. The intention of commit29bb45f25f(regmap-mmio: Use native endianness for read/write) was to fix this by making regmap default to native endianness but this breaks most other MMIO users where the hardware has a fixed endianness and the implementation uses the __raw accessors which are not intended to be used outside of architecture code. Instead use the newly added native-endian DT property to say exactly what we want for these systems. Fixes:29bb45f25f(regmap-mmio: Use native endianness for read/write) Reported-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org>
96 lines
1.6 KiB
Plaintext
96 lines
1.6 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm6328";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <160000000>;
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cpu@0 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <1>;
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};
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};
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clocks {
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periph_clk: periph_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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};
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aliases {
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leds0 = &leds0;
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uart0 = &uart0;
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};
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cpu_intc: cpu_intc {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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ubus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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periph_intc: periph_intc@10000020 {
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compatible = "brcm,bcm3380-l2-intc";
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reg = <0x10000024 0x4 0x1000002c 0x4>,
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<0x10000020 0x4 0x10000028 0x4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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uart0: serial@10000100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000100 0x18>;
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interrupt-parent = <&periph_intc>;
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interrupts = <28>;
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clocks = <&periph_clk>;
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status = "disabled";
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};
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timer: timer@10000040 {
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compatible = "syscon";
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reg = <0x10000040 0x2c>;
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native-endian;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&timer>;
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offset = <0x28>;
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mask = <0x1>;
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};
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leds0: led-controller@10000800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm6328-leds";
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reg = <0x10000800 0x24>;
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status = "disabled";
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};
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};
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};
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