mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
66c6b856d8
For yet unknown reason 4-bit mode doesn't work on MPC8569E-MDS boards, so make 1-bit mode default. When we resolve the issue, u-boot will remove sdhci,1-bit-only property from the device tree, while SDHCI will still work with older u-boots. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
670 lines
17 KiB
Plaintext
670 lines
17 KiB
Plaintext
/*
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* MPC8569E MDS Device Tree Source
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*
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* Copyright (C) 2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8569EMDS";
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compatible = "fsl,MPC8569EMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet5 = &enet5;
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ethernet7 = &enet7;
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pci1 = &pci1;
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rapidio0 = &rio0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8569@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0xf8000000 0x00008000
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0x2 0x0 0xf0000000 0x04000000
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0x3 0x0 0xfc000000 0x00008000
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0x4 0x0 0xf8008000 0x00008000
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0x5 0x0 0xf8010000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x02000000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0 {
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label = "ramdisk";
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reg = <0x00000000 0x01c00000>;
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};
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partition@1c00000 {
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label = "kernel";
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reg = <0x01c00000 0x002e0000>;
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};
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partiton@1ee0000 {
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label = "dtb";
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reg = <0x01ee0000 0x00020000>;
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};
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partition@1f00000 {
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label = "firmware";
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reg = <0x01f00000 0x00080000>;
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read-only;
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};
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partition@1f80000 {
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label = "u-boot";
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reg = <0x01f80000 0x00080000>;
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read-only;
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};
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};
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bcsr@1,0 {
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compatible = "fsl,mpc8569mds-bcsr";
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reg = <1 0 0x8000>;
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};
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nand@3,0 {
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compatible = "fsl,mpc8569-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <3 0 0x8000>;
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};
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pib@4,0 {
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compatible = "fsl,mpc8569mds-pib";
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reg = <4 0 0x8000>;
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};
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pib@5,0 {
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compatible = "fsl,mpc8569mds-pib";
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reg = <5 0 0x8000>;
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};
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8569-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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bus-frequency = <0>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8569-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8569-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8569-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8569-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8569-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8569-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8569-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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sdhci@2e000 {
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compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <72 0x8>;
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interrupt-parent = <&mpic>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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status = "disabled";
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sdhci,1-bit-only;
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};
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crypto@30000 {
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compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
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"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 58 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xbfe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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msi@41600 {
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compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8569-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x100>;
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ranges = <0x0 0xe0100 0x100>;
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device_type = "par_io";
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num-ports = <7>;
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qe_pio_e: gpio-controller@80 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8569-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x80 0x18>;
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gpio-controller;
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};
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
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0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
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0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
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0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
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0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
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0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
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0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
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0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
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0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
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0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
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0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
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0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
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0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
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0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
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0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
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};
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pio3: ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
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0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
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0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
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0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
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0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
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0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
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0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
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0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
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0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
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0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
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0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
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0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
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0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
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};
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pio4: ucc_pin@04 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
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0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
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0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
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0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
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0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
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0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
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0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
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0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
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0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
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0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
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0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
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0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
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0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
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};
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};
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};
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qe@e0080000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0080000 0x40000>;
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reg = <0xe0080000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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fsl,qe-num-riscs = <4>;
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fsl,qe-num-snums = <46>;
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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interrupts = <46 2 46 2>; //high:30 low:30
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interrupt-parent = <&mpic>;
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};
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spi@4c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
|
|
reg = <0x4c0 0x40>;
|
|
cell-index = <0>;
|
|
interrupts = <2>;
|
|
interrupt-parent = <&qeic>;
|
|
gpios = <&qe_pio_e 30 0>;
|
|
mode = "cpu-qe";
|
|
|
|
serial-flash@0 {
|
|
compatible = "stm,m25p40";
|
|
reg = <0>;
|
|
spi-max-frequency = <25000000>;
|
|
};
|
|
};
|
|
|
|
spi@500 {
|
|
cell-index = <1>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x500 0x40>;
|
|
interrupts = <1>;
|
|
interrupt-parent = <&qeic>;
|
|
mode = "cpu";
|
|
};
|
|
|
|
enet0: ucc@2000 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <1>;
|
|
reg = <0x2000 0x200>;
|
|
interrupts = <32>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk12";
|
|
pio-handle = <&pio1>;
|
|
phy-handle = <&qe_phy0>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
mdio@2120 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x2120 0x18>;
|
|
compatible = "fsl,ucc-mdio";
|
|
|
|
qe_phy0: ethernet-phy@07 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <1 1>;
|
|
reg = <0x7>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy1: ethernet-phy@01 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <2 1>;
|
|
reg = <0x1>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy2: ethernet-phy@02 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <3 1>;
|
|
reg = <0x2>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy3: ethernet-phy@03 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <4 1>;
|
|
reg = <0x3>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy5: ethernet-phy@04 {
|
|
interrupt-parent = <&mpic>;
|
|
reg = <0x04>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy7: ethernet-phy@06 {
|
|
interrupt-parent = <&mpic>;
|
|
reg = <0x6>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
};
|
|
mdio@3520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x3520 0x18>;
|
|
compatible = "fsl,ucc-mdio";
|
|
|
|
tbi0: tbi-phy@15 {
|
|
reg = <0x15>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
mdio@3720 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x3720 0x38>;
|
|
compatible = "fsl,ucc-mdio";
|
|
tbi1: tbi-phy@17 {
|
|
reg = <0x17>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
|
|
enet2: ucc@2200 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <3>;
|
|
reg = <0x2200 0x200>;
|
|
interrupts = <34>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk12";
|
|
pio-handle = <&pio3>;
|
|
phy-handle = <&qe_phy2>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
enet1: ucc@3000 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <2>;
|
|
reg = <0x3000 0x200>;
|
|
interrupts = <33>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk17";
|
|
pio-handle = <&pio2>;
|
|
phy-handle = <&qe_phy1>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
enet3: ucc@3200 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <4>;
|
|
reg = <0x3200 0x200>;
|
|
interrupts = <35>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk17";
|
|
pio-handle = <&pio4>;
|
|
phy-handle = <&qe_phy3>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
enet5: ucc@3400 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <6>;
|
|
reg = <0x3400 0x200>;
|
|
interrupts = <41>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "none";
|
|
tbi-handle = <&tbi0>;
|
|
phy-handle = <&qe_phy5>;
|
|
phy-connection-type = "sgmii";
|
|
};
|
|
|
|
enet7: ucc@3600 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <8>;
|
|
reg = <0x3600 0x200>;
|
|
interrupts = <43>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "none";
|
|
tbi-handle = <&tbi1>;
|
|
phy-handle = <&qe_phy7>;
|
|
phy-connection-type = "sgmii";
|
|
};
|
|
|
|
muram@10000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
|
ranges = <0x0 0x10000 0x20000>;
|
|
|
|
data-only@0 {
|
|
compatible = "fsl,qe-muram-data",
|
|
"fsl,cpm-muram-data";
|
|
reg = <0x0 0x20000>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
/* PCI Express */
|
|
pci1: pcie@e000a000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe000a000 0x1000>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 (PEX) */
|
|
00000 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
00000 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
00000 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
|
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
|
0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
|
|
clock-frequency = <33333333>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x10000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x800000>;
|
|
};
|
|
};
|
|
|
|
rio0: rapidio@e00c00000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
|
|
reg = <0xe00c0000 0x20000>;
|
|
ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
|
|
interrupts = <48 2 /* error */
|
|
49 2 /* bell_outb */
|
|
50 2 /* bell_inb */
|
|
53 2 /* msg1_tx */
|
|
54 2 /* msg1_rx */
|
|
55 2 /* msg2_tx */
|
|
56 2 /* msg2_rx */>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
};
|