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c8ffbd433a
After MFC v8.0, mfc f/w lets the driver know how much scratch buffer size is required for decoder. If mfc f/w has the functionality, E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size is required for encoder too. Signed-off-by: Smitha T Murthy <smitha.t@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/*
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* Register definition file for Samsung MFC V8.x Interface (FIMV) driver
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _REGS_MFC_V8_H
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#define _REGS_MFC_V8_H
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#include <linux/sizes.h>
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#include "regs-mfc-v7.h"
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/* Additional registers for v8 */
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#define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104
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#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108
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#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144
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#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148
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#define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150
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#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138
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#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c
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#define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160
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#define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260
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#define S5P_FIMV_D_MV_BUFFER_V8 0xf460
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#define S5P_FIMV_D_NUM_MV_V8 0xf134
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#define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154
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#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560
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#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564
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#define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0
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#define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4
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#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc
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#define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0
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#define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4
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#define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0
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/* Display information register */
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#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600
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#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604
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/* Display status */
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#define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608
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#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c
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#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610
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#define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618
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#define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c
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#define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620
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#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624
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/* Decoded picture information register */
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#define S5P_FIMV_D_DECODED_STATUS_V8 0xf644
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#define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648
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#define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c
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#define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650
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#define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654
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#define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664
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/* Returned value register for specific setting */
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#define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674
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#define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678
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#define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8
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/* SEI related information */
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#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc
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/* Encoder Registers */
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#define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf794
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#define S5P_FIMV_E_RC_CONFIG_V8 0xf798
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#define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c
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#define S5P_FIMV_E_RC_RPARAM_V8 0xf7a4
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#define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a8
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#define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac
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#define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b4
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#define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b8
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#define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c
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#define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790
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#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf894
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#define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c
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#define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50
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#define S5P_FIMV_E_H264_OPTIONS_V8 0xfb54
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/* MFCv8 Context buffer sizes */
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#define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */
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#define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */
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#define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */
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#define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */
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#define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */
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/* Buffer size defines */
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#define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \
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(((w) * 576 + (h) * 128) + 4128)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \
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(((w) * 592) + 2336)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \
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(((w) * 576) + 10512 + \
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((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))
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#define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \
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((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \
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+ (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))
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/* BUffer alignment defines */
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#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64
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/* MFCv8 variant defines */
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#define MAX_FW_SIZE_V8 (SZ_512K) /* 512KB */
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#define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */
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#define MFC_VERSION_V8 0x80
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#define MFC_NUM_PORTS_V8 1
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#endif /*_REGS_MFC_V8_H*/
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