mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 21:26:39 +07:00
e4745fef55
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org>
486 lines
12 KiB
C
486 lines
12 KiB
C
/*
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* Broadcom BCM63xx SPI controller support
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*
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* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
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* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/pm_runtime.h>
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#include <bcm63xx_dev_spi.h>
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#define BCM63XX_SPI_MAX_PREPEND 15
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struct bcm63xx_spi {
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struct completion done;
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void __iomem *regs;
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int irq;
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/* Platform data */
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unsigned fifo_size;
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unsigned int msg_type_shift;
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unsigned int msg_ctl_width;
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/* data iomem */
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u8 __iomem *tx_io;
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const u8 __iomem *rx_io;
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struct clk *clk;
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struct platform_device *pdev;
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};
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static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
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unsigned int offset)
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{
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return bcm_readb(bs->regs + bcm63xx_spireg(offset));
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}
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static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
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unsigned int offset)
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{
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return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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}
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static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
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u8 value, unsigned int offset)
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{
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bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
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}
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static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
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u16 value, unsigned int offset)
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{
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bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
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}
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static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
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{ 20000000, SPI_CLK_20MHZ },
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{ 12500000, SPI_CLK_12_50MHZ },
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{ 6250000, SPI_CLK_6_250MHZ },
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{ 3125000, SPI_CLK_3_125MHZ },
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{ 1563000, SPI_CLK_1_563MHZ },
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{ 781000, SPI_CLK_0_781MHZ },
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{ 391000, SPI_CLK_0_391MHZ }
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};
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static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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u8 clk_cfg, reg;
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int i;
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/* Find the closest clock configuration */
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for (i = 0; i < SPI_CLK_MASK; i++) {
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if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
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clk_cfg = bcm63xx_spi_freq_table[i][1];
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break;
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}
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}
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/* No matching configuration found, default to lowest */
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if (i == SPI_CLK_MASK)
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clk_cfg = SPI_CLK_0_391MHZ;
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/* clear existing clock configuration bits of the register */
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reg = bcm_spi_readb(bs, SPI_CLK_CFG);
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reg &= ~SPI_CLK_MASK;
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reg |= clk_cfg;
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bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
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dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
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clk_cfg, t->speed_hz);
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA)
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static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
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unsigned int num_transfers)
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{
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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u16 msg_ctl;
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u16 cmd;
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u8 rx_tail;
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unsigned int i, timeout = 0, prepend_len = 0, len = 0;
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struct spi_transfer *t = first;
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bool do_rx = false;
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bool do_tx = false;
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/* Disable the CMD_DONE interrupt */
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bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
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t->tx_buf, t->rx_buf, t->len);
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if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
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prepend_len = t->len;
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/* prepare the buffer */
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for (i = 0; i < num_transfers; i++) {
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if (t->tx_buf) {
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do_tx = true;
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memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
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/* don't prepend more than one tx */
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if (t != first)
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prepend_len = 0;
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}
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if (t->rx_buf) {
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do_rx = true;
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/* prepend is half-duplex write only */
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if (t == first)
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prepend_len = 0;
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}
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len += t->len;
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t = list_entry(t->transfer_list.next, struct spi_transfer,
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transfer_list);
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}
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reinit_completion(&bs->done);
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/* Fill in the Message control register */
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msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
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if (do_rx && do_tx && prepend_len == 0)
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msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
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else if (do_rx)
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msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
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else if (do_tx)
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msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
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switch (bs->msg_ctl_width) {
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case 8:
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bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
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break;
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case 16:
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bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
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break;
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}
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/* Issue the transfer */
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cmd = SPI_CMD_START_IMMEDIATE;
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cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
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bcm_spi_writew(bs, cmd, SPI_CMD);
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/* Enable the CMD_DONE interrupt */
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bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
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timeout = wait_for_completion_timeout(&bs->done, HZ);
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if (!timeout)
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return -ETIMEDOUT;
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if (!do_rx)
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return 0;
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len = 0;
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t = first;
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/* Read out all the data */
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for (i = 0; i < num_transfers; i++) {
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if (t->rx_buf)
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memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
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if (t != first || prepend_len == 0)
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len += t->len;
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t = list_entry(t->transfer_list.next, struct spi_transfer,
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transfer_list);
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}
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return 0;
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}
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static int bcm63xx_spi_transfer_one(struct spi_master *master,
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struct spi_message *m)
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{
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struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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struct spi_transfer *t, *first = NULL;
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struct spi_device *spi = m->spi;
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int status = 0;
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unsigned int n_transfers = 0, total_len = 0;
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bool can_use_prepend = false;
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/*
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* This SPI controller does not support keeping CS active after a
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* transfer.
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* Work around this by merging as many transfers we can into one big
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* full-duplex transfers.
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*/
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (!first)
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first = t;
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n_transfers++;
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total_len += t->len;
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if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
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first->len <= BCM63XX_SPI_MAX_PREPEND)
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can_use_prepend = true;
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else if (can_use_prepend && t->tx_buf)
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can_use_prepend = false;
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/* we can only transfer one fifo worth of data */
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if ((can_use_prepend &&
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total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
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(!can_use_prepend && total_len > bs->fifo_size)) {
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dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
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total_len, bs->fifo_size);
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status = -EINVAL;
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goto exit;
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}
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/* all combined transfers have to have the same speed */
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if (t->speed_hz != first->speed_hz) {
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dev_err(&spi->dev, "unable to change speed between transfers\n");
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status = -EINVAL;
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goto exit;
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}
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/* CS will be deasserted directly after transfer */
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if (t->delay_usecs) {
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dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
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status = -EINVAL;
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goto exit;
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}
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if (t->cs_change ||
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list_is_last(&t->transfer_list, &m->transfers)) {
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/* configure adapter for a new transfer */
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bcm63xx_spi_setup_transfer(spi, first);
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/* send the data */
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status = bcm63xx_txrx_bufs(spi, first, n_transfers);
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if (status)
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goto exit;
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m->actual_length += total_len;
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first = NULL;
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n_transfers = 0;
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total_len = 0;
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can_use_prepend = false;
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}
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}
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exit:
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m->status = status;
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spi_finalize_current_message(master);
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return 0;
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}
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/* This driver supports single master mode only. Hence
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* CMD_DONE is the only interrupt we care about
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*/
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static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = (struct spi_master *)dev_id;
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struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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u8 intr;
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/* Read interupts and clear them immediately */
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intr = bcm_spi_readb(bs, SPI_INT_STATUS);
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bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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/* A transfer completed */
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if (intr & SPI_INTR_CMD_DONE)
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complete(&bs->done);
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return IRQ_HANDLED;
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}
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static int bcm63xx_spi_probe(struct platform_device *pdev)
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{
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struct resource *r;
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struct device *dev = &pdev->dev;
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struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
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int irq;
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struct spi_master *master;
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struct clk *clk;
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struct bcm63xx_spi *bs;
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int ret;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "no irq\n");
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return -ENXIO;
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}
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clk = devm_clk_get(dev, "spi");
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if (IS_ERR(clk)) {
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dev_err(dev, "no clock for device\n");
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return PTR_ERR(clk);
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}
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master = spi_alloc_master(dev, sizeof(*bs));
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if (!master) {
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dev_err(dev, "out of memory\n");
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return -ENOMEM;
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}
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bs = spi_master_get_devdata(master);
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init_completion(&bs->done);
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platform_set_drvdata(pdev, master);
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bs->pdev = pdev;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bs->regs = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(bs->regs)) {
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ret = PTR_ERR(bs->regs);
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goto out_err;
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}
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bs->irq = irq;
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bs->clk = clk;
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bs->fifo_size = pdata->fifo_size;
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ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
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pdev->name, master);
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if (ret) {
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dev_err(dev, "unable to request irq\n");
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goto out_err;
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}
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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master->transfer_one_message = bcm63xx_spi_transfer_one;
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master->mode_bits = MODEBITS;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->auto_runtime_pm = true;
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bs->msg_type_shift = pdata->msg_type_shift;
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bs->msg_ctl_width = pdata->msg_ctl_width;
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bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
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bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
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switch (bs->msg_ctl_width) {
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case 8:
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case 16:
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break;
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default:
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dev_err(dev, "unsupported MSG_CTL width: %d\n",
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bs->msg_ctl_width);
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goto out_err;
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}
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/* Initialize hardware */
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ret = clk_prepare_enable(bs->clk);
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if (ret)
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goto out_err;
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bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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/* register and we are done */
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ret = devm_spi_register_master(dev, master);
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if (ret) {
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dev_err(dev, "spi register failed\n");
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goto out_clk_disable;
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}
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dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
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r->start, irq, bs->fifo_size);
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return 0;
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out_clk_disable:
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clk_disable_unprepare(clk);
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out_err:
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spi_master_put(master);
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return ret;
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}
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static int bcm63xx_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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/* reset spi block */
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bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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/* HW shutdown */
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clk_disable_unprepare(bs->clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int bcm63xx_spi_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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spi_master_suspend(master);
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clk_disable_unprepare(bs->clk);
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return 0;
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}
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static int bcm63xx_spi_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct bcm63xx_spi *bs = spi_master_get_devdata(master);
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int ret;
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ret = clk_prepare_enable(bs->clk);
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if (ret)
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return ret;
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spi_master_resume(master);
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return 0;
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}
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#endif
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static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
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};
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static struct platform_driver bcm63xx_spi_driver = {
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.driver = {
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.name = "bcm63xx-spi",
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.owner = THIS_MODULE,
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.pm = &bcm63xx_spi_pm_ops,
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},
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.probe = bcm63xx_spi_probe,
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.remove = bcm63xx_spi_remove,
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};
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module_platform_driver(bcm63xx_spi_driver);
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MODULE_ALIAS("platform:bcm63xx_spi");
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MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
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MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
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MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
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MODULE_LICENSE("GPL");
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