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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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190dc2e684
The Zynq GPIO controller does not disable the interrupt detection when the interrupt is masked and only disables the propagation of the interrupt. This means when the controller detects an interrupt condition while the interrupt is logically disabled (and masked) it will propagate the recorded interrupt event once the interrupt is enabled. This will cause the interrupt consumer to see spurious interrupts to prevent this first make sure that the interrupt is not asserted and then enable it. E.g. when a interrupt is requested with request_irq() it will be configured according to the requested type (edge/level triggered, etc.) after that it will be enabled. But the detection circuit might have already registered a false interrupt before the interrupt type was correctly configured and once the interrupt is unmasked this false interrupt will be propagated and the interrupt handler for the just request interrupt will called. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
693 lines
20 KiB
C
693 lines
20 KiB
C
/*
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* Xilinx Zynq GPIO device driver
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any later
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* version.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#define DRIVER_NAME "zynq-gpio"
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/* Maximum banks */
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#define ZYNQ_GPIO_MAX_BANK 4
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#define ZYNQ_GPIO_BANK0_NGPIO 32
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#define ZYNQ_GPIO_BANK1_NGPIO 22
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#define ZYNQ_GPIO_BANK2_NGPIO 32
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#define ZYNQ_GPIO_BANK3_NGPIO 32
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#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
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ZYNQ_GPIO_BANK1_NGPIO + \
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ZYNQ_GPIO_BANK2_NGPIO + \
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ZYNQ_GPIO_BANK3_NGPIO)
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#define ZYNQ_GPIO_BANK0_PIN_MIN 0
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#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
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ZYNQ_GPIO_BANK0_NGPIO - 1)
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#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
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ZYNQ_GPIO_BANK1_NGPIO - 1)
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#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
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ZYNQ_GPIO_BANK2_NGPIO - 1)
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#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
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ZYNQ_GPIO_BANK3_NGPIO - 1)
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/* Register offsets for the GPIO device */
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/* LSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
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/* MSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
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/* Data Register-RW */
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#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
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/* Direction mode reg-RW */
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#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
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/* Output enable reg-RW */
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#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
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/* Interrupt mask reg-RO */
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#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
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/* Interrupt enable reg-WO */
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#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
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/* Interrupt disable reg-WO */
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#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
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/* Interrupt status reg-RO */
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#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
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/* Interrupt type reg-RW */
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#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
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/* Interrupt polarity reg-RW */
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#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
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/* Interrupt on any, reg-RW */
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#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
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/* Disable all interrupts mask */
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#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
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/* Mid pin number of a bank */
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#define ZYNQ_GPIO_MID_PIN_NUM 16
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/* GPIO upper 16 bit mask */
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#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
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/**
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* struct zynq_gpio - gpio device private data structure
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* @chip: instance of the gpio_chip
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* @base_addr: base address of the GPIO device
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* @clk: clock resource for this controller
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*/
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struct zynq_gpio {
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struct gpio_chip chip;
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void __iomem *base_addr;
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struct clk *clk;
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};
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/**
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* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
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* for a given pin in the GPIO device
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* @pin_num: gpio pin number within the device
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* @bank_num: an output parameter used to return the bank number of the gpio
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* pin
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* @bank_pin_num: an output parameter used to return pin number within a bank
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* for the given gpio pin
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*
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* Returns the bank number and pin offset within the bank.
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*/
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static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
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unsigned int *bank_num,
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unsigned int *bank_pin_num)
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{
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switch (pin_num) {
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case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
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*bank_num = 0;
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*bank_pin_num = pin_num;
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break;
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case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
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*bank_num = 1;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
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break;
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case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
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*bank_num = 2;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
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break;
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case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
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*bank_num = 3;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
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break;
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default:
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WARN(true, "invalid GPIO pin number: %u", pin_num);
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*bank_num = 0;
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*bank_pin_num = 0;
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break;
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}
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}
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/**
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* zynq_gpio_get_value - Get the state of the specified pin of GPIO device
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* @chip: gpio_chip instance to be worked on
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* @pin: gpio pin number within the device
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*
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* This function reads the state of the specified pin of the GPIO device.
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*
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* Return: 0 if the pin is low, 1 if pin is high.
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*/
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static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
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{
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u32 data;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
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data = readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
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return (data >> bank_pin_num) & 1;
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}
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/**
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* zynq_gpio_set_value - Modify the state of the pin with specified value
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* @chip: gpio_chip instance to be worked on
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* @pin: gpio pin number within the device
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* @state: value used to modify the state of the specified pin
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*
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* This function calculates the register offset (i.e to lower 16 bits or
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* upper 16 bits) based on the given pin number and sets the state of a
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* gpio pin to the specified value. The state is either 0 or non-zero.
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*/
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static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
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int state)
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{
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unsigned int reg_offset, bank_num, bank_pin_num;
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struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
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if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
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/* only 16 data bits in bit maskable reg */
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bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
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reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
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} else {
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reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
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}
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/*
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* get the 32 bit value to be written to the mask/data register where
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* the upper 16 bits is the mask and lower 16 bits is the data
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*/
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state = !!state;
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state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
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((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
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writel_relaxed(state, gpio->base_addr + reg_offset);
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}
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/**
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* zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
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* @chip: gpio_chip instance to be worked on
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* @pin: gpio pin number within the device
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*
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* This function uses the read-modify-write sequence to set the direction of
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* the gpio pin as input.
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*
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* Return: 0 always
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*/
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static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
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/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
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if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
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return -EINVAL;
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/* clear the bit in direction mode reg to set the pin as input */
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg &= ~BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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return 0;
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}
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/**
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* zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
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* @chip: gpio_chip instance to be worked on
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* @pin: gpio pin number within the device
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* @state: value to be written to specified pin
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*
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* This function sets the direction of specified GPIO pin as output, configures
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* the Output Enable register for the pin and uses zynq_gpio_set to set
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* the state of the pin to the value specified.
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*
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* Return: 0 always
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*/
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static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
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int state)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
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/* set the GPIO pin as output */
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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/* configure the output enable reg for the pin */
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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/* set the state of the pin */
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zynq_gpio_set_value(chip, pin, state);
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return 0;
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}
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/**
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* zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
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* @irq_data: per irq and chip data passed down to chip functions
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*
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* This function calculates gpio pin number from irq number and sets the
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* bit in the Interrupt Disable register of the corresponding bank to disable
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* interrupts for that pin.
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*/
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static void zynq_gpio_irq_mask(struct irq_data *irq_data)
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{
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unsigned int device_pin_num, bank_num, bank_pin_num;
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struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
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device_pin_num = irq_data->hwirq;
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zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
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writel_relaxed(BIT(bank_pin_num),
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gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
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}
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/**
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* zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
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* @irq_data: irq data containing irq number of gpio pin for the interrupt
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* to enable
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*
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* This function calculates the gpio pin number from irq number and sets the
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* bit in the Interrupt Enable register of the corresponding bank to enable
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* interrupts for that pin.
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*/
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static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
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{
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unsigned int device_pin_num, bank_num, bank_pin_num;
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struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
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device_pin_num = irq_data->hwirq;
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zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
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writel_relaxed(BIT(bank_pin_num),
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gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
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}
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/**
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* zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
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* @irq_data: irq data containing irq number of gpio pin for the interrupt
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* to ack
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*
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* This function calculates gpio pin number from irq number and sets the bit
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* in the Interrupt Status Register of the corresponding bank, to ACK the irq.
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*/
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static void zynq_gpio_irq_ack(struct irq_data *irq_data)
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{
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unsigned int device_pin_num, bank_num, bank_pin_num;
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struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
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device_pin_num = irq_data->hwirq;
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zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
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writel_relaxed(BIT(bank_pin_num),
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gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
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}
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/**
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* zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
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* @irq_data: irq data containing irq number of gpio pin for the interrupt
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* to enable
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*
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* Clears the INTSTS bit and unmasks the given interrrupt.
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*/
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static void zynq_gpio_irq_enable(struct irq_data *irq_data)
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{
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/*
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* The Zynq GPIO controller does not disable interrupt detection when
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* the interrupt is masked and only disables the propagation of the
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* interrupt. This means when the controller detects an interrupt
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* condition while the interrupt is logically disabled it will propagate
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* that interrupt event once the interrupt is enabled. This will cause
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* the interrupt consumer to see spurious interrupts to prevent this
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* first make sure that the interrupt is not asserted and then enable
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* it.
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*/
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zynq_gpio_irq_ack(irq_data);
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zynq_gpio_irq_unmask(irq_data);
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}
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/**
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* zynq_gpio_set_irq_type - Set the irq type for a gpio pin
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* @irq_data: irq data containing irq number of gpio pin
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* @type: interrupt type that is to be set for the gpio pin
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*
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* This function gets the gpio pin number and its bank from the gpio pin number
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* and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
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*
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* Return: 0, negative error otherwise.
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* TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
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* TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
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* TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
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* TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
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* TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
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*/
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static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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{
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u32 int_type, int_pol, int_any;
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unsigned int device_pin_num, bank_num, bank_pin_num;
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struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
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device_pin_num = irq_data->hwirq;
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zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
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int_type = readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
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int_pol = readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
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int_any = readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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/*
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* based on the type requested, configure the INT_TYPE, INT_POLARITY
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* and INT_ANY registers
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*/
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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int_type |= BIT(bank_pin_num);
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int_pol |= BIT(bank_pin_num);
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int_any &= ~BIT(bank_pin_num);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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int_type |= BIT(bank_pin_num);
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int_pol &= ~BIT(bank_pin_num);
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int_any &= ~BIT(bank_pin_num);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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int_type |= BIT(bank_pin_num);
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int_any |= BIT(bank_pin_num);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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int_type &= ~BIT(bank_pin_num);
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int_pol |= BIT(bank_pin_num);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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int_type &= ~BIT(bank_pin_num);
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int_pol &= ~BIT(bank_pin_num);
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(int_type,
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gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
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writel_relaxed(int_pol,
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gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
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writel_relaxed(int_any,
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gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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|
return 0;
|
|
}
|
|
|
|
static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
|
|
{
|
|
if (on)
|
|
zynq_gpio_irq_unmask(data);
|
|
else
|
|
zynq_gpio_irq_mask(data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* irq chip descriptor */
|
|
static struct irq_chip zynq_gpio_irqchip = {
|
|
.name = DRIVER_NAME,
|
|
.irq_enable = zynq_gpio_irq_enable,
|
|
.irq_mask = zynq_gpio_irq_mask,
|
|
.irq_unmask = zynq_gpio_irq_unmask,
|
|
.irq_set_type = zynq_gpio_set_irq_type,
|
|
.irq_set_wake = zynq_gpio_set_wake,
|
|
};
|
|
|
|
/**
|
|
* zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
|
|
* @irq: irq number of the gpio bank where interrupt has occurred
|
|
* @desc: irq descriptor instance of the 'irq'
|
|
*
|
|
* This function reads the Interrupt Status Register of each bank to get the
|
|
* gpio pin number which has triggered an interrupt. It then acks the triggered
|
|
* interrupt and calls the pin specific handler set by the higher layer
|
|
* application for that pin.
|
|
* Note: A bug is reported if no handler is set for the gpio pin.
|
|
*/
|
|
static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
u32 int_sts, int_enb;
|
|
unsigned int bank_num;
|
|
struct zynq_gpio *gpio = irq_get_handler_data(irq);
|
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
|
|
|
chained_irq_enter(irqchip, desc);
|
|
|
|
for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) {
|
|
int_sts = readl_relaxed(gpio->base_addr +
|
|
ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
|
|
int_enb = readl_relaxed(gpio->base_addr +
|
|
ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
|
|
int_sts &= ~int_enb;
|
|
if (int_sts) {
|
|
int offset;
|
|
unsigned long pending = int_sts;
|
|
|
|
for_each_set_bit(offset, &pending, 32) {
|
|
unsigned int gpio_irq =
|
|
irq_find_mapping(gpio->chip.irqdomain,
|
|
offset);
|
|
generic_handle_irq(gpio_irq);
|
|
}
|
|
|
|
/* clear IRQ in HW */
|
|
writel_relaxed(int_sts, gpio->base_addr +
|
|
ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
|
|
}
|
|
}
|
|
|
|
chained_irq_exit(irqchip, desc);
|
|
}
|
|
|
|
static int __maybe_unused zynq_gpio_suspend(struct device *dev)
|
|
{
|
|
if (!device_may_wakeup(dev))
|
|
return pm_runtime_force_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused zynq_gpio_resume(struct device *dev)
|
|
{
|
|
if (!device_may_wakeup(dev))
|
|
return pm_runtime_force_resume(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct zynq_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
|
clk_disable_unprepare(gpio->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct zynq_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
|
return clk_prepare_enable(gpio->clk);
|
|
}
|
|
|
|
static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(chip->dev);
|
|
|
|
/*
|
|
* If the device is already active pm_runtime_get() will return 1 on
|
|
* success, but gpio_request still needs to return 0.
|
|
*/
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
pm_runtime_put(chip->dev);
|
|
}
|
|
|
|
static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
|
|
SET_PM_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
|
|
zynq_gpio_runtime_resume, NULL)
|
|
};
|
|
|
|
/**
|
|
* zynq_gpio_probe - Initialization method for a zynq_gpio device
|
|
* @pdev: platform device instance
|
|
*
|
|
* This function allocates memory resources for the gpio device and registers
|
|
* all the banks of the device. It will also set up interrupts for the gpio
|
|
* pins.
|
|
* Note: Interrupts are disabled for all the banks during initialization.
|
|
*
|
|
* Return: 0 on success, negative error otherwise.
|
|
*/
|
|
static int zynq_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
int ret, bank_num, irq;
|
|
struct zynq_gpio *gpio;
|
|
struct gpio_chip *chip;
|
|
struct resource *res;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
if (!gpio)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, gpio);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(gpio->base_addr))
|
|
return PTR_ERR(gpio->base_addr);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "invalid IRQ\n");
|
|
return irq;
|
|
}
|
|
|
|
/* configure the gpio chip */
|
|
chip = &gpio->chip;
|
|
chip->label = "zynq_gpio";
|
|
chip->owner = THIS_MODULE;
|
|
chip->dev = &pdev->dev;
|
|
chip->get = zynq_gpio_get_value;
|
|
chip->set = zynq_gpio_set_value;
|
|
chip->request = zynq_gpio_request;
|
|
chip->free = zynq_gpio_free;
|
|
chip->direction_input = zynq_gpio_dir_in;
|
|
chip->direction_output = zynq_gpio_dir_out;
|
|
chip->base = -1;
|
|
chip->ngpio = ZYNQ_GPIO_NR_GPIOS;
|
|
|
|
/* Enable GPIO clock */
|
|
gpio->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(gpio->clk)) {
|
|
dev_err(&pdev->dev, "input clock not found.\n");
|
|
return PTR_ERR(gpio->clk);
|
|
}
|
|
ret = clk_prepare_enable(gpio->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to enable clock.\n");
|
|
return ret;
|
|
}
|
|
|
|
/* report a bug if gpio chip registration fails */
|
|
ret = gpiochip_add(chip);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to add gpio chip\n");
|
|
goto err_disable_clk;
|
|
}
|
|
|
|
/* disable interrupts for all banks */
|
|
for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++)
|
|
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
|
|
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
|
|
|
|
ret = gpiochip_irqchip_add(chip, &zynq_gpio_irqchip, 0,
|
|
handle_simple_irq, IRQ_TYPE_NONE);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to add irq chip\n");
|
|
goto err_rm_gpiochip;
|
|
}
|
|
|
|
gpiochip_set_chained_irqchip(chip, &zynq_gpio_irqchip, irq,
|
|
zynq_gpio_irqhandler);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
device_set_wakeup_capable(&pdev->dev, 1);
|
|
|
|
return 0;
|
|
|
|
err_rm_gpiochip:
|
|
if (gpiochip_remove(chip))
|
|
dev_err(&pdev->dev, "Failed to remove gpio chip\n");
|
|
err_disable_clk:
|
|
clk_disable_unprepare(gpio->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* zynq_gpio_remove - Driver removal function
|
|
* @pdev: platform device instance
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int zynq_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct zynq_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
ret = gpiochip_remove(&gpio->chip);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to remove gpio chip\n");
|
|
return ret;
|
|
}
|
|
clk_disable_unprepare(gpio->clk);
|
|
device_set_wakeup_capable(&pdev->dev, 0);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id zynq_gpio_of_match[] = {
|
|
{ .compatible = "xlnx,zynq-gpio-1.0", },
|
|
{ /* end of table */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
|
|
|
|
static struct platform_driver zynq_gpio_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.pm = &zynq_gpio_dev_pm_ops,
|
|
.of_match_table = zynq_gpio_of_match,
|
|
},
|
|
.probe = zynq_gpio_probe,
|
|
.remove = zynq_gpio_remove,
|
|
};
|
|
|
|
/**
|
|
* zynq_gpio_init - Initial driver registration call
|
|
*
|
|
* Return: value from platform_driver_register
|
|
*/
|
|
static int __init zynq_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&zynq_gpio_driver);
|
|
}
|
|
postcore_initcall(zynq_gpio_init);
|
|
|
|
MODULE_AUTHOR("Xilinx Inc.");
|
|
MODULE_DESCRIPTION("Zynq GPIO driver");
|
|
MODULE_LICENSE("GPL");
|