mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 19:16:40 +07:00
9f5132ae82
Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
450 lines
11 KiB
C
450 lines
11 KiB
C
/*
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* Emma Mobile GPIO Support - GIO
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*
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* Copyright (C) 2012 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/gpio-em.h>
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struct em_gio_priv {
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void __iomem *base0;
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void __iomem *base1;
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spinlock_t sense_lock;
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struct platform_device *pdev;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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};
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#define GIO_E1 0x00
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#define GIO_E0 0x04
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#define GIO_EM 0x04
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#define GIO_OL 0x08
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#define GIO_OH 0x0c
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#define GIO_I 0x10
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#define GIO_IIA 0x14
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#define GIO_IEN 0x18
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#define GIO_IDS 0x1c
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#define GIO_IIM 0x1c
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#define GIO_RAW 0x20
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#define GIO_MST 0x24
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#define GIO_IIR 0x28
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#define GIO_IDT0 0x40
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#define GIO_IDT1 0x44
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#define GIO_IDT2 0x48
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#define GIO_IDT3 0x4c
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#define GIO_RAWBL 0x50
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#define GIO_RAWBH 0x54
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#define GIO_IRBL 0x58
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#define GIO_IRBH 0x5c
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#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
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static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
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{
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if (offs < GIO_IDT0)
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return ioread32(p->base0 + offs);
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else
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return ioread32(p->base1 + (offs - GIO_IDT0));
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}
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static inline void em_gio_write(struct em_gio_priv *p, int offs,
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unsigned long value)
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{
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if (offs < GIO_IDT0)
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iowrite32(value, p->base0 + offs);
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else
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iowrite32(value, p->base1 + (offs - GIO_IDT0));
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}
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static void em_gio_irq_disable(struct irq_data *d)
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{
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struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
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em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
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}
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static void em_gio_irq_enable(struct irq_data *d)
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{
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struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
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em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
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}
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static int em_gio_irq_reqres(struct irq_data *d)
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{
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struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
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if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
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dev_err(p->gpio_chip.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return -EINVAL;
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}
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return 0;
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}
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static void em_gio_irq_relres(struct irq_data *d)
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{
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struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
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gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
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}
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#define GIO_ASYNC(x) (x + 8)
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static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
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[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
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[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
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[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
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[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
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};
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static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
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struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
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unsigned int reg, offset, shift;
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unsigned long flags;
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unsigned long tmp;
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if (!value)
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return -EINVAL;
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offset = irqd_to_hwirq(d);
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pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
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/* 8 x 4 bit fields in 4 IDT registers */
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reg = GIO_IDT(offset >> 3);
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shift = (offset & 0x07) << 4;
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spin_lock_irqsave(&p->sense_lock, flags);
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/* disable the interrupt in IIA */
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tmp = em_gio_read(p, GIO_IIA);
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tmp &= ~BIT(offset);
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em_gio_write(p, GIO_IIA, tmp);
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/* change the sense setting in IDT */
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tmp = em_gio_read(p, reg);
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tmp &= ~(0xf << shift);
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tmp |= value << shift;
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em_gio_write(p, reg, tmp);
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/* clear pending interrupts */
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em_gio_write(p, GIO_IIR, BIT(offset));
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/* enable the interrupt in IIA */
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tmp = em_gio_read(p, GIO_IIA);
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tmp |= BIT(offset);
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em_gio_write(p, GIO_IIA, tmp);
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spin_unlock_irqrestore(&p->sense_lock, flags);
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return 0;
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}
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static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
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{
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struct em_gio_priv *p = dev_id;
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unsigned long pending;
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unsigned int offset, irqs_handled = 0;
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while ((pending = em_gio_read(p, GIO_MST))) {
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offset = __ffs(pending);
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em_gio_write(p, GIO_IIR, BIT(offset));
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generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
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irqs_handled++;
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}
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return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
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}
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static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
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{
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return container_of(chip, struct em_gio_priv, gpio_chip);
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}
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static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
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return 0;
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}
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static int em_gio_get(struct gpio_chip *chip, unsigned offset)
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{
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return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
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}
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static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
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unsigned shift, int value)
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{
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/* upper 16 bits contains mask and lower 16 actual value */
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em_gio_write(gpio_to_priv(chip), reg,
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(BIT(shift + 16)) | (value << shift));
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}
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static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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/* output is split into two registers */
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if (offset < 16)
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__em_gio_set(chip, GIO_OL, offset, value);
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else
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__em_gio_set(chip, GIO_OH, offset - 16, value);
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}
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static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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/* write GPIO value to output before selecting output mode of pin */
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em_gio_set(chip, offset, value);
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em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
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return 0;
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}
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static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
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}
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static int em_gio_request(struct gpio_chip *chip, unsigned offset)
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{
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return pinctrl_request_gpio(chip->base + offset);
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}
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static void em_gio_free(struct gpio_chip *chip, unsigned offset)
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{
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pinctrl_free_gpio(chip->base + offset);
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/* Set the GPIO as an input to ensure that the next GPIO request won't
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* drive the GPIO pin as an output.
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*/
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em_gio_direction_input(chip, offset);
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}
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static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct em_gio_priv *p = h->host_data;
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pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
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irq_set_chip_data(irq, h->host_data);
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irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID); /* kill me now */
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return 0;
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}
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static struct irq_domain_ops em_gio_irq_domain_ops = {
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.map = em_gio_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int em_gio_probe(struct platform_device *pdev)
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{
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struct gpio_em_config pdata_dt;
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struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
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struct em_gio_priv *p;
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struct resource *io[2], *irq[2];
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struct gpio_chip *gpio_chip;
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struct irq_chip *irq_chip;
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const char *name = dev_name(&pdev->dev);
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int ret;
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p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
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if (!p) {
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ret = -ENOMEM;
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goto err0;
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}
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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spin_lock_init(&p->sense_lock);
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io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
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if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
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dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
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ret = -EINVAL;
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goto err0;
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}
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p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
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resource_size(io[0]));
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if (!p->base0) {
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dev_err(&pdev->dev, "failed to remap low I/O memory\n");
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ret = -ENXIO;
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goto err0;
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}
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p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
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resource_size(io[1]));
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if (!p->base1) {
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dev_err(&pdev->dev, "failed to remap high I/O memory\n");
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ret = -ENXIO;
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goto err0;
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}
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if (!pdata) {
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memset(&pdata_dt, 0, sizeof(pdata_dt));
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pdata = &pdata_dt;
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if (of_property_read_u32(pdev->dev.of_node, "ngpios",
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&pdata->number_of_pins)) {
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dev_err(&pdev->dev, "Missing ngpios OF property\n");
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ret = -EINVAL;
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goto err0;
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}
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ret = of_alias_get_id(pdev->dev.of_node, "gpio");
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if (ret < 0) {
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dev_err(&pdev->dev, "Couldn't get OF id\n");
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goto err0;
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}
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pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
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}
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gpio_chip = &p->gpio_chip;
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gpio_chip->of_node = pdev->dev.of_node;
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gpio_chip->direction_input = em_gio_direction_input;
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gpio_chip->get = em_gio_get;
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gpio_chip->direction_output = em_gio_direction_output;
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gpio_chip->set = em_gio_set;
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gpio_chip->to_irq = em_gio_to_irq;
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gpio_chip->request = em_gio_request;
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gpio_chip->free = em_gio_free;
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gpio_chip->label = name;
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gpio_chip->dev = &pdev->dev;
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gpio_chip->owner = THIS_MODULE;
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gpio_chip->base = pdata->gpio_base;
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gpio_chip->ngpio = pdata->number_of_pins;
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irq_chip = &p->irq_chip;
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irq_chip->name = name;
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irq_chip->irq_mask = em_gio_irq_disable;
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irq_chip->irq_unmask = em_gio_irq_enable;
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irq_chip->irq_set_type = em_gio_irq_set_type;
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irq_chip->irq_request_resources = em_gio_irq_reqres;
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irq_chip->irq_release_resources = em_gio_irq_relres;
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irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
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p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
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pdata->number_of_pins,
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pdata->irq_base,
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&em_gio_irq_domain_ops, p);
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if (!p->irq_domain) {
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ret = -ENXIO;
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dev_err(&pdev->dev, "cannot initialize irq domain\n");
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goto err0;
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}
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if (devm_request_irq(&pdev->dev, irq[0]->start,
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em_gio_irq_handler, 0, name, p)) {
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dev_err(&pdev->dev, "failed to request low IRQ\n");
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ret = -ENOENT;
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goto err1;
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}
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if (devm_request_irq(&pdev->dev, irq[1]->start,
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em_gio_irq_handler, 0, name, p)) {
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dev_err(&pdev->dev, "failed to request high IRQ\n");
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ret = -ENOENT;
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goto err1;
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}
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ret = gpiochip_add(gpio_chip);
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if (ret) {
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dev_err(&pdev->dev, "failed to add GPIO controller\n");
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goto err1;
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}
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if (pdata->pctl_name) {
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ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
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gpio_chip->base, gpio_chip->ngpio);
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if (ret < 0)
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dev_warn(&pdev->dev, "failed to add pin range\n");
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}
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return 0;
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err1:
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irq_domain_remove(p->irq_domain);
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err0:
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return ret;
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}
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static int em_gio_remove(struct platform_device *pdev)
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{
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struct em_gio_priv *p = platform_get_drvdata(pdev);
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gpiochip_remove(&p->gpio_chip);
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irq_domain_remove(p->irq_domain);
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return 0;
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}
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static const struct of_device_id em_gio_dt_ids[] = {
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{ .compatible = "renesas,em-gio", },
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{},
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};
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MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
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static struct platform_driver em_gio_device_driver = {
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.probe = em_gio_probe,
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.remove = em_gio_remove,
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.driver = {
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.name = "em_gio",
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.of_match_table = em_gio_dt_ids,
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.owner = THIS_MODULE,
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}
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};
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static int __init em_gio_init(void)
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{
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return platform_driver_register(&em_gio_device_driver);
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}
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postcore_initcall(em_gio_init);
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static void __exit em_gio_exit(void)
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{
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platform_driver_unregister(&em_gio_device_driver);
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}
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module_exit(em_gio_exit);
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MODULE_AUTHOR("Magnus Damm");
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MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
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MODULE_LICENSE("GPL v2");
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