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65d0cf0be7
Map shared data structure that will hold CPU registers, VPMU context, V/PCPU IDs of the CPU interrupted by PMU interrupt. Hypervisor fills this information in its handler and passes it to the guest for further processing. Set up PMU VIRQ. Now that perf infrastructure will assume that PMU is available on a PV guest we need to be careful and make sure that accesses via RDPMC instruction don't cause fatal traps by the hypervisor. Provide a nop RDPMC handler. For the same reason avoid issuing a warning on a write to APIC's LVTPC. Both of these will be made functional in later patches. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com> |
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| .. | ||
| hvm | ||
| io | ||
| callback.h | ||
| elfnote.h | ||
| event_channel.h | ||
| features.h | ||
| grant_table.h | ||
| memory.h | ||
| nmi.h | ||
| physdev.h | ||
| platform.h | ||
| sched.h | ||
| vcpu.h | ||
| version.h | ||
| xen-mca.h | ||
| xen.h | ||
| xenpmu.h | ||