mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 22:20:56 +07:00
d03a93bbec
For OMAP4 devices, timers 5-8 have both a L3 bus address and a Cortex-A9 private bus address. Currently the device-tree source only contains the L3 bus address for these timers. Update these timers to include the Cortex-A9 private address and make the default address the Cortex-A9 private bus address to match the current HWMOD implementation. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
534 lines
12 KiB
Plaintext
534 lines
12 KiB
Plaintext
/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Carveout for multimedia usecases
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* It should be the last 48MB of the first 512MB memory part
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* In theory, it should not even exist. That zone should be reserved
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* dynamically during the .reserve callback.
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*/
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/memreserve/ 0x9d000000 0x03000000;
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/include/ "skeleton.dtsi"
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/ {
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compatible = "ti,omap4430", "ti,omap4";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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};
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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};
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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};
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L2: l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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local-timer@0x48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x48240600 0x20>;
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interrupts = <1 13 0x304>;
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};
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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};
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dsp {
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compatible = "ti,omap3-c64";
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ti,hwmods = "dsp";
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};
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iva {
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compatible = "ti,ivahd";
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ti,hwmods = "iva";
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP4 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since that will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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counter32k: counter@4a304000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4a304000 0x20>;
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ti,hwmods = "counter_32k";
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};
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omap4_pmx_core: pinmux@4a100040 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4a100040 0x0196>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap4_pmx_wkup: pinmux@4a31e040 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4a31e040 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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gpio1: gpio@4a310000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4a310000 0x200>;
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interrupts = <0 29 0x4>;
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ti,hwmods = "gpio1";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@48055000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48055000 0x200>;
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interrupts = <0 30 0x4>;
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@48057000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48057000 0x200>;
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interrupts = <0 31 0x4>;
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio4: gpio@48059000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48059000 0x200>;
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interrupts = <0 32 0x4>;
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio5: gpio@4805b000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805b000 0x200>;
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interrupts = <0 33 0x4>;
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio6: gpio@4805d000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805d000 0x200>;
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interrupts = <0 34 0x4>;
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ti,hwmods = "gpio6";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806a000 0x100>;
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interrupts = <0 72 0x4>;
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806c000 0x100>;
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interrupts = <0 73 0x4>;
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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};
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uart3: serial@48020000 {
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compatible = "ti,omap4-uart";
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reg = <0x48020000 0x100>;
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interrupts = <0 74 0x4>;
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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};
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uart4: serial@4806e000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806e000 0x100>;
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interrupts = <0 70 0x4>;
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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};
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i2c1: i2c@48070000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48070000 0x100>;
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interrupts = <0 56 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48072000 0x100>;
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interrupts = <0 57 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c2";
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};
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i2c3: i2c@48060000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48060000 0x100>;
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interrupts = <0 61 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c3";
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};
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i2c4: i2c@48350000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48350000 0x100>;
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interrupts = <0 62 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c4";
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};
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mcspi1: spi@48098000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x48098000 0x200>;
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interrupts = <0 65 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi1";
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ti,spi-num-cs = <4>;
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};
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mcspi2: spi@4809a000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x4809a000 0x200>;
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interrupts = <0 66 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi2";
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ti,spi-num-cs = <2>;
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};
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mcspi3: spi@480b8000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x480b8000 0x200>;
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interrupts = <0 91 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi3";
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ti,spi-num-cs = <2>;
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};
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mcspi4: spi@480ba000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x480ba000 0x200>;
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interrupts = <0 48 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi4";
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ti,spi-num-cs = <1>;
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};
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mmc1: mmc@4809c000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x4809c000 0x400>;
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interrupts = <0 83 0x4>;
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ti,hwmods = "mmc1";
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ti,dual-volt;
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ti,needs-special-reset;
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};
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mmc2: mmc@480b4000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x480b4000 0x400>;
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interrupts = <0 86 0x4>;
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ti,hwmods = "mmc2";
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ti,needs-special-reset;
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};
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mmc3: mmc@480ad000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x480ad000 0x400>;
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interrupts = <0 94 0x4>;
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ti,hwmods = "mmc3";
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ti,needs-special-reset;
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};
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mmc4: mmc@480d1000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x480d1000 0x400>;
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interrupts = <0 96 0x4>;
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ti,hwmods = "mmc4";
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ti,needs-special-reset;
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};
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mmc5: mmc@480d5000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x480d5000 0x400>;
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interrupts = <0 59 0x4>;
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ti,hwmods = "mmc5";
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ti,needs-special-reset;
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};
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wdt2: wdt@4a314000 {
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compatible = "ti,omap4-wdt", "ti,omap3-wdt";
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reg = <0x4a314000 0x80>;
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interrupts = <0 80 0x4>;
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ti,hwmods = "wd_timer2";
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};
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mcpdm: mcpdm@40132000 {
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compatible = "ti,omap4-mcpdm";
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reg = <0x40132000 0x7f>, /* MPU private access */
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<0x49032000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <0 112 0x4>;
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ti,hwmods = "mcpdm";
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};
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dmic: dmic@4012e000 {
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compatible = "ti,omap4-dmic";
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reg = <0x4012e000 0x7f>, /* MPU private access */
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<0x4902e000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <0 114 0x4>;
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ti,hwmods = "dmic";
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};
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mcbsp1: mcbsp@40122000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40122000 0xff>, /* MPU private access */
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<0x49022000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <0 17 0x4>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp1";
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};
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mcbsp2: mcbsp@40124000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40124000 0xff>, /* MPU private access */
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<0x49024000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <0 22 0x4>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp2";
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};
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mcbsp3: mcbsp@40126000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40126000 0xff>, /* MPU private access */
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<0x49026000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <0 23 0x4>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp3";
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};
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mcbsp4: mcbsp@48096000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x48096000 0xff>; /* L4 Interconnect */
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reg-names = "mpu";
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interrupts = <0 16 0x4>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp4";
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};
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keypad: keypad@4a31c000 {
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compatible = "ti,omap4-keypad";
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reg = <0x4a31c000 0x80>;
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interrupts = <0 120 0x4>;
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reg-names = "mpu";
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ti,hwmods = "kbd";
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};
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emif1: emif@4c000000 {
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compatible = "ti,emif-4d";
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reg = <0x4c000000 0x100>;
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interrupts = <0 110 0x4>;
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ti,hwmods = "emif1";
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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emif2: emif@4d000000 {
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compatible = "ti,emif-4d";
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reg = <0x4d000000 0x100>;
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interrupts = <0 111 0x4>;
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ti,hwmods = "emif2";
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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ocp2scp@4a0ad000 {
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compatible = "ti,omap-ocp2scp";
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reg = <0x4a0ad000 0x1f>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "ocp2scp_usb_phy";
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};
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timer1: timer@4a318000 {
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compatible = "ti,omap2-timer";
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reg = <0x4a318000 0x80>;
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interrupts = <0 37 0x4>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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};
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timer2: timer@48032000 {
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compatible = "ti,omap2-timer";
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reg = <0x48032000 0x80>;
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interrupts = <0 38 0x4>;
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ti,hwmods = "timer2";
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};
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timer3: timer@48034000 {
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compatible = "ti,omap2-timer";
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reg = <0x48034000 0x80>;
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interrupts = <0 39 0x4>;
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ti,hwmods = "timer3";
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};
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timer4: timer@48036000 {
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compatible = "ti,omap2-timer";
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reg = <0x48036000 0x80>;
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interrupts = <0 40 0x4>;
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ti,hwmods = "timer4";
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};
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timer5: timer@40138000 {
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compatible = "ti,omap2-timer";
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reg = <0x40138000 0x80>,
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<0x49038000 0x80>;
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interrupts = <0 41 0x4>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@4013a000 {
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compatible = "ti,omap2-timer";
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reg = <0x4013a000 0x80>,
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<0x4903a000 0x80>;
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interrupts = <0 42 0x4>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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};
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timer7: timer@4013c000 {
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compatible = "ti,omap2-timer";
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reg = <0x4013c000 0x80>,
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<0x4903c000 0x80>;
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interrupts = <0 43 0x4>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@4013e000 {
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compatible = "ti,omap2-timer";
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reg = <0x4013e000 0x80>,
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<0x4903e000 0x80>;
|
|
interrupts = <0 44 0x4>;
|
|
ti,hwmods = "timer8";
|
|
ti,timer-pwm;
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer9: timer@4803e000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4803e000 0x80>;
|
|
interrupts = <0 45 0x4>;
|
|
ti,hwmods = "timer9";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer10: timer@48086000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48086000 0x80>;
|
|
interrupts = <0 46 0x4>;
|
|
ti,hwmods = "timer10";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer11: timer@48088000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48088000 0x80>;
|
|
interrupts = <0 47 0x4>;
|
|
ti,hwmods = "timer11";
|
|
ti,timer-pwm;
|
|
};
|
|
};
|
|
};
|