mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
4585945bf1
The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
329 lines
9.1 KiB
C
329 lines
9.1 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_MT8173_H
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#define _DT_BINDINGS_CLK_MT8173_H
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/* TOPCKGEN */
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#define CLK_TOP_CLKPH_MCK_O 1
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#define CLK_TOP_USB_SYSPLL_125M 3
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#define CLK_TOP_HDMITX_DIG_CTS 4
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#define CLK_TOP_ARMCA7PLL_754M 5
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#define CLK_TOP_ARMCA7PLL_502M 6
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#define CLK_TOP_MAIN_H546M 7
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#define CLK_TOP_MAIN_H364M 8
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#define CLK_TOP_MAIN_H218P4M 9
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#define CLK_TOP_MAIN_H156M 10
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#define CLK_TOP_TVDPLL_445P5M 11
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#define CLK_TOP_TVDPLL_594M 12
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#define CLK_TOP_UNIV_624M 13
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#define CLK_TOP_UNIV_416M 14
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#define CLK_TOP_UNIV_249P6M 15
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#define CLK_TOP_UNIV_178P3M 16
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#define CLK_TOP_UNIV_48M 17
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#define CLK_TOP_CLKRTC_EXT 18
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#define CLK_TOP_CLKRTC_INT 19
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#define CLK_TOP_FPC 20
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#define CLK_TOP_HDMITXPLL_D2 21
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#define CLK_TOP_HDMITXPLL_D3 22
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#define CLK_TOP_ARMCA7PLL_D2 23
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#define CLK_TOP_ARMCA7PLL_D3 24
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#define CLK_TOP_APLL1 25
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#define CLK_TOP_APLL2 26
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#define CLK_TOP_DMPLL 27
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#define CLK_TOP_DMPLL_D2 28
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#define CLK_TOP_DMPLL_D4 29
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#define CLK_TOP_DMPLL_D8 30
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#define CLK_TOP_DMPLL_D16 31
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#define CLK_TOP_LVDSPLL_D2 32
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#define CLK_TOP_LVDSPLL_D4 33
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#define CLK_TOP_LVDSPLL_D8 34
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#define CLK_TOP_MMPLL 35
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#define CLK_TOP_MMPLL_D2 36
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#define CLK_TOP_MSDCPLL 37
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#define CLK_TOP_MSDCPLL_D2 38
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#define CLK_TOP_MSDCPLL_D4 39
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#define CLK_TOP_MSDCPLL2 40
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#define CLK_TOP_MSDCPLL2_D2 41
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#define CLK_TOP_MSDCPLL2_D4 42
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#define CLK_TOP_SYSPLL_D2 43
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#define CLK_TOP_SYSPLL1_D2 44
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#define CLK_TOP_SYSPLL1_D4 45
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#define CLK_TOP_SYSPLL1_D8 46
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#define CLK_TOP_SYSPLL1_D16 47
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#define CLK_TOP_SYSPLL_D3 48
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#define CLK_TOP_SYSPLL2_D2 49
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#define CLK_TOP_SYSPLL2_D4 50
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#define CLK_TOP_SYSPLL_D5 51
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#define CLK_TOP_SYSPLL3_D2 52
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#define CLK_TOP_SYSPLL3_D4 53
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#define CLK_TOP_SYSPLL_D7 54
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#define CLK_TOP_SYSPLL4_D2 55
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#define CLK_TOP_SYSPLL4_D4 56
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#define CLK_TOP_TVDPLL 57
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#define CLK_TOP_TVDPLL_D2 58
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#define CLK_TOP_TVDPLL_D4 59
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#define CLK_TOP_TVDPLL_D8 60
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#define CLK_TOP_TVDPLL_D16 61
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#define CLK_TOP_UNIVPLL_D2 62
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#define CLK_TOP_UNIVPLL1_D2 63
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#define CLK_TOP_UNIVPLL1_D4 64
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#define CLK_TOP_UNIVPLL1_D8 65
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#define CLK_TOP_UNIVPLL_D3 66
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#define CLK_TOP_UNIVPLL2_D2 67
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#define CLK_TOP_UNIVPLL2_D4 68
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#define CLK_TOP_UNIVPLL2_D8 69
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#define CLK_TOP_UNIVPLL_D5 70
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#define CLK_TOP_UNIVPLL3_D2 71
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#define CLK_TOP_UNIVPLL3_D4 72
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#define CLK_TOP_UNIVPLL3_D8 73
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#define CLK_TOP_UNIVPLL_D7 74
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#define CLK_TOP_UNIVPLL_D26 75
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#define CLK_TOP_UNIVPLL_D52 76
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#define CLK_TOP_VCODECPLL 77
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#define CLK_TOP_VCODECPLL_370P5 78
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#define CLK_TOP_VENCPLL 79
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#define CLK_TOP_VENCPLL_D2 80
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#define CLK_TOP_VENCPLL_D4 81
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#define CLK_TOP_AXI_SEL 82
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#define CLK_TOP_MEM_SEL 83
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#define CLK_TOP_DDRPHYCFG_SEL 84
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#define CLK_TOP_MM_SEL 85
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#define CLK_TOP_PWM_SEL 86
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#define CLK_TOP_VDEC_SEL 87
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#define CLK_TOP_VENC_SEL 88
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#define CLK_TOP_MFG_SEL 89
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#define CLK_TOP_CAMTG_SEL 90
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#define CLK_TOP_UART_SEL 91
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#define CLK_TOP_SPI_SEL 92
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#define CLK_TOP_USB20_SEL 93
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#define CLK_TOP_USB30_SEL 94
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#define CLK_TOP_MSDC50_0_H_SEL 95
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#define CLK_TOP_MSDC50_0_SEL 96
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#define CLK_TOP_MSDC30_1_SEL 97
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#define CLK_TOP_MSDC30_2_SEL 98
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#define CLK_TOP_MSDC30_3_SEL 99
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#define CLK_TOP_AUDIO_SEL 100
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#define CLK_TOP_AUD_INTBUS_SEL 101
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#define CLK_TOP_PMICSPI_SEL 102
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#define CLK_TOP_SCP_SEL 103
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#define CLK_TOP_ATB_SEL 104
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#define CLK_TOP_VENC_LT_SEL 105
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#define CLK_TOP_DPI0_SEL 106
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#define CLK_TOP_IRDA_SEL 107
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#define CLK_TOP_CCI400_SEL 108
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#define CLK_TOP_AUD_1_SEL 109
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#define CLK_TOP_AUD_2_SEL 110
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#define CLK_TOP_MEM_MFG_IN_SEL 111
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#define CLK_TOP_AXI_MFG_IN_SEL 112
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#define CLK_TOP_SCAM_SEL 113
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#define CLK_TOP_SPINFI_IFR_SEL 114
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#define CLK_TOP_HDMI_SEL 115
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#define CLK_TOP_DPILVDS_SEL 116
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#define CLK_TOP_MSDC50_2_H_SEL 117
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#define CLK_TOP_HDCP_SEL 118
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#define CLK_TOP_HDCP_24M_SEL 119
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#define CLK_TOP_RTC_SEL 120
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#define CLK_TOP_APLL1_DIV0 121
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#define CLK_TOP_APLL1_DIV1 122
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#define CLK_TOP_APLL1_DIV2 123
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#define CLK_TOP_APLL1_DIV3 124
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#define CLK_TOP_APLL1_DIV4 125
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#define CLK_TOP_APLL1_DIV5 126
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#define CLK_TOP_APLL2_DIV0 127
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#define CLK_TOP_APLL2_DIV1 128
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#define CLK_TOP_APLL2_DIV2 129
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#define CLK_TOP_APLL2_DIV3 130
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#define CLK_TOP_APLL2_DIV4 131
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#define CLK_TOP_APLL2_DIV5 132
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#define CLK_TOP_I2S0_M_SEL 133
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#define CLK_TOP_I2S1_M_SEL 134
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#define CLK_TOP_I2S2_M_SEL 135
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#define CLK_TOP_I2S3_M_SEL 136
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#define CLK_TOP_I2S3_B_SEL 137
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#define CLK_TOP_DSI0_DIG 138
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#define CLK_TOP_DSI1_DIG 139
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#define CLK_TOP_LVDS_PXL 140
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#define CLK_TOP_LVDS_CTS 141
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#define CLK_TOP_NR_CLK 142
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/* APMIXED_SYS */
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#define CLK_APMIXED_ARMCA15PLL 1
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#define CLK_APMIXED_ARMCA7PLL 2
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#define CLK_APMIXED_MAINPLL 3
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#define CLK_APMIXED_UNIVPLL 4
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#define CLK_APMIXED_MMPLL 5
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#define CLK_APMIXED_MSDCPLL 6
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#define CLK_APMIXED_VENCPLL 7
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#define CLK_APMIXED_TVDPLL 8
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#define CLK_APMIXED_MPLL 9
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#define CLK_APMIXED_VCODECPLL 10
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#define CLK_APMIXED_APLL1 11
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#define CLK_APMIXED_APLL2 12
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#define CLK_APMIXED_LVDSPLL 13
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#define CLK_APMIXED_MSDCPLL2 14
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#define CLK_APMIXED_REF2USB_TX 15
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#define CLK_APMIXED_HDMI_REF 16
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#define CLK_APMIXED_NR_CLK 17
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/* INFRA_SYS */
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#define CLK_INFRA_DBGCLK 1
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#define CLK_INFRA_SMI 2
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#define CLK_INFRA_AUDIO 3
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#define CLK_INFRA_GCE 4
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#define CLK_INFRA_L2C_SRAM 5
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#define CLK_INFRA_M4U 6
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#define CLK_INFRA_CPUM 7
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#define CLK_INFRA_KP 8
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#define CLK_INFRA_CEC 9
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#define CLK_INFRA_PMICSPI 10
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#define CLK_INFRA_PMICWRAP 11
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#define CLK_INFRA_CLK_13M 12
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#define CLK_INFRA_NR_CLK 13
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/* PERI_SYS */
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#define CLK_PERI_NFI 1
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#define CLK_PERI_THERM 2
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#define CLK_PERI_PWM1 3
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#define CLK_PERI_PWM2 4
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#define CLK_PERI_PWM3 5
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#define CLK_PERI_PWM4 6
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#define CLK_PERI_PWM5 7
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#define CLK_PERI_PWM6 8
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#define CLK_PERI_PWM7 9
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#define CLK_PERI_PWM 10
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#define CLK_PERI_USB0 11
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#define CLK_PERI_USB1 12
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#define CLK_PERI_AP_DMA 13
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#define CLK_PERI_MSDC30_0 14
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#define CLK_PERI_MSDC30_1 15
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#define CLK_PERI_MSDC30_2 16
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#define CLK_PERI_MSDC30_3 17
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#define CLK_PERI_NLI_ARB 18
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#define CLK_PERI_IRDA 19
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#define CLK_PERI_UART0 20
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#define CLK_PERI_UART1 21
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#define CLK_PERI_UART2 22
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#define CLK_PERI_UART3 23
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#define CLK_PERI_I2C0 24
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#define CLK_PERI_I2C1 25
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#define CLK_PERI_I2C2 26
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#define CLK_PERI_I2C3 27
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#define CLK_PERI_I2C4 28
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#define CLK_PERI_AUXADC 29
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#define CLK_PERI_SPI0 30
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#define CLK_PERI_I2C5 31
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#define CLK_PERI_NFIECC 32
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#define CLK_PERI_SPI 33
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#define CLK_PERI_IRRX 34
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#define CLK_PERI_I2C6 35
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#define CLK_PERI_UART0_SEL 36
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#define CLK_PERI_UART1_SEL 37
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#define CLK_PERI_UART2_SEL 38
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#define CLK_PERI_UART3_SEL 39
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#define CLK_PERI_NR_CLK 40
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/* IMG_SYS */
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#define CLK_IMG_LARB2_SMI 1
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#define CLK_IMG_CAM_SMI 2
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#define CLK_IMG_CAM_CAM 3
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#define CLK_IMG_SEN_TG 4
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#define CLK_IMG_SEN_CAM 5
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#define CLK_IMG_CAM_SV 6
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#define CLK_IMG_FD 7
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#define CLK_IMG_NR_CLK 8
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/* MM_SYS */
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#define CLK_MM_SMI_COMMON 1
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#define CLK_MM_SMI_LARB0 2
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#define CLK_MM_CAM_MDP 3
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#define CLK_MM_MDP_RDMA0 4
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#define CLK_MM_MDP_RDMA1 5
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#define CLK_MM_MDP_RSZ0 6
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#define CLK_MM_MDP_RSZ1 7
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#define CLK_MM_MDP_RSZ2 8
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#define CLK_MM_MDP_TDSHP0 9
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#define CLK_MM_MDP_TDSHP1 10
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#define CLK_MM_MDP_WDMA 11
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#define CLK_MM_MDP_WROT0 12
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#define CLK_MM_MDP_WROT1 13
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#define CLK_MM_FAKE_ENG 14
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#define CLK_MM_MUTEX_32K 15
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#define CLK_MM_DISP_OVL0 16
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#define CLK_MM_DISP_OVL1 17
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#define CLK_MM_DISP_RDMA0 18
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#define CLK_MM_DISP_RDMA1 19
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#define CLK_MM_DISP_RDMA2 20
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#define CLK_MM_DISP_WDMA0 21
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#define CLK_MM_DISP_WDMA1 22
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#define CLK_MM_DISP_COLOR0 23
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#define CLK_MM_DISP_COLOR1 24
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#define CLK_MM_DISP_AAL 25
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#define CLK_MM_DISP_GAMMA 26
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#define CLK_MM_DISP_UFOE 27
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#define CLK_MM_DISP_SPLIT0 28
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#define CLK_MM_DISP_SPLIT1 29
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#define CLK_MM_DISP_MERGE 30
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#define CLK_MM_DISP_OD 31
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#define CLK_MM_DISP_PWM0MM 32
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#define CLK_MM_DISP_PWM026M 33
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#define CLK_MM_DISP_PWM1MM 34
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#define CLK_MM_DISP_PWM126M 35
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#define CLK_MM_DSI0_ENGINE 36
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#define CLK_MM_DSI0_DIGITAL 37
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#define CLK_MM_DSI1_ENGINE 38
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#define CLK_MM_DSI1_DIGITAL 39
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#define CLK_MM_DPI_PIXEL 40
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#define CLK_MM_DPI_ENGINE 41
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#define CLK_MM_DPI1_PIXEL 42
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#define CLK_MM_DPI1_ENGINE 43
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#define CLK_MM_HDMI_PIXEL 44
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#define CLK_MM_HDMI_PLLCK 45
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#define CLK_MM_HDMI_AUDIO 46
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#define CLK_MM_HDMI_SPDIF 47
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#define CLK_MM_LVDS_PIXEL 48
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#define CLK_MM_LVDS_CTS 49
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#define CLK_MM_SMI_LARB4 50
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#define CLK_MM_HDMI_HDCP 51
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#define CLK_MM_HDMI_HDCP24M 52
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#define CLK_MM_NR_CLK 53
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/* VDEC_SYS */
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#define CLK_VDEC_CKEN 1
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#define CLK_VDEC_LARB_CKEN 2
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#define CLK_VDEC_NR_CLK 3
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/* VENC_SYS */
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#define CLK_VENC_CKE0 1
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#define CLK_VENC_CKE1 2
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#define CLK_VENC_CKE2 3
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#define CLK_VENC_CKE3 4
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#define CLK_VENC_NR_CLK 5
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/* VENCLT_SYS */
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#define CLK_VENCLT_CKE0 1
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#define CLK_VENCLT_CKE1 2
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#define CLK_VENCLT_NR_CLK 3
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#endif /* _DT_BINDINGS_CLK_MT8173_H */
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