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bf4348e622
r8a7791 (R-Car H2) SoC and its Koelsch board and, r8a7740 (R-Mobile A1) SoC and its Armadillo800eva board * Set CPU clock frequency from OF nodes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTdV6AAAoJENfPZGlqN0++Q70QAI4sQTJdB6WRbmQ5DtAVQZ4n lJcFNoL4HkH52b9vC5GrHAZmtvJl4s5n53qAi88gsdkznfHmsDcFdbG7GdOo4ij0 JHE6aPHEhpOMjLJaYwN6Sr+X3sIQFktjRKzREFuUVYrVnFiVWSLksnmBF9EmiRma IdWXSZhHAENnPHMC3IuYbfIRtRKXyNLvpW3SloMdtE4C1gc0PWA3yG2a28gFQfI1 aQZ3z4m5eocxABpUClP1PVMVFWSr8dqfK9PIriGGPJBuLGsKCmqWiWLX3rXNxK/S VaU3UYOscXVV33SAI3VRGtUi7Eh3PfPXmlKSsQDBjZKfnhwlwIztekzuZcq+vaK+ FLYFRh8DlpxqIA2fl2B8D6C5kpsgTbWKGUhEKi9UgXFqM1ZEm3SxyYFaN8NckyQP t7ZH3ZKNfjJrPk6bN5JUC7eepRiNtc7YOz5d1I4HBQkrFpIFlc+JHTODX0R6Ao4+ 9mSraY+5Boyrw9aOTDH2wY08M01eYipN99zeScPZ/rNXEx+McwWHXBOhemrkKhbr 6cWHFeJoR7V1UuibV9ifLlvsBl+j/IGv0B8ZjgwaYN+KLxI/OWAigUfNvkvP3zp8 xMLgyvqTHh8gFU24xdPbhZ1DJNM5rQSOKd4AIGqiPS4ZGHZ4Ash7BtS42cA43RiG TWoNYzKKNvcGDP67HmyI =pLjF -----END PGP SIGNATURE----- Merge tag 'renesas-soc-cleanup-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC soc-cleanup Updates for v3.16" from Simon Horman: r8a7791 (R-Car H2) SoC and its Koelsch board and, r8a7740 (R-Mobile A1) SoC and its Armadillo800eva board * Set CPU clock frequency from OF nodes * tag 'renesas-soc-cleanup-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Set clock frequency in HZ from OF nodes ARM: shmobile: Use shmobile_init_late() on r8a7740 ARM: shmobile: Remove unused r8a7791_init_early() ARM: shmobile: Use r8a7791 DT CPU Frequency for Koelsch ARM: shmobile: Use r8a7791 DT CPU Frequency in common case ARM: shmobile: Remove unused r8a7740_init_delay() ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT Ref ARM: shmobile: Use r8a7740 DT CPU Frequency in common case ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTS Signed-off-by: Olof Johansson <olof@lixom.net>
230 lines
6.0 KiB
Plaintext
230 lines
6.0 KiB
Plaintext
/*
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* Device Tree Source for the r8a7740 SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7740";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x0>;
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clock-frequency = <800000000>;
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};
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};
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gic: interrupt-controller@c2800000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xc2800000 0x1000>,
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<0xc2000000 0x1000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin0: IRQ0 - IRQ7 */
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irqpin0: irqpin@e6900000 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900000 4>,
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<0xe6900010 4>,
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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interrupt-parent = <&gic>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin1: IRQ8 - IRQ15 */
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irqpin1: irqpin@e6900004 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900004 4>,
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<0xe6900014 4>,
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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interrupt-parent = <&gic>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin2: IRQ16 - IRQ23 */
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irqpin2: irqpin@e6900008 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900008 4>,
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<0xe6900018 4>,
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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interrupt-parent = <&gic>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin3: IRQ24 - IRQ31 */
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irqpin3: irqpin@e690000c {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe690000c 4>,
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<0xe690001c 4>,
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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interrupt-parent = <&gic>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c0: i2c@fff20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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reg = <0xfff20000 0x425>;
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interrupt-parent = <&gic>;
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interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c1: i2c@e6c20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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reg = <0xe6c20000 0x425>;
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interrupt-parent = <&gic>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
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0 71 IRQ_TYPE_LEVEL_HIGH
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pfc: pfc@e6050000 {
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compatible = "renesas,pfc-r8a7740";
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reg = <0xe6050000 0x8000>,
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<0xe605800c 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts-extended =
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<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
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<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
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<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
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<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
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<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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};
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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mmcif0: mmc@e6bd0000 {
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compatible = "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdhi0: sd@e6850000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6850000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi1: sd@e6860000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6860000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi2: sd@e6870000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6870000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sh_fsi2: sound@fe1f0000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,sh_fsi2";
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reg = <0xfe1f0000 0x400>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0x4>;
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status = "disabled";
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};
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};
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