mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 07:02:59 +07:00
829ec6408d
The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. struct spi_nor_flash_parameter is filled at run-time with info gathered from flash_info, manufacturer and sfdp data. struct spi_nor_flash_parameter should be opaque to the SPI NOR controller drivers, make sure it is. spi_nor_option_flags, spi_nor_read_command, spi_nor_pp_command, spi_nor_read_command_index and spi_nor_pp_command_index are defined for the core use, make sure they are opaque to the SPI NOR controller drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
60 lines
2.1 KiB
C
60 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2005, Intec Automation Inc.
|
|
* Copyright (C) 2014, Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#include <linux/mtd/spi-nor.h>
|
|
|
|
#include "core.h"
|
|
|
|
static void gd25q256_default_init(struct spi_nor *nor)
|
|
{
|
|
/*
|
|
* Some manufacturer like GigaDevice may use different
|
|
* bit to set QE on different memories, so the MFR can't
|
|
* indicate the quad_enable method for this case, we need
|
|
* to set it in the default_init fixup hook.
|
|
*/
|
|
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
|
|
}
|
|
|
|
static struct spi_nor_fixups gd25q256_fixups = {
|
|
.default_init = gd25q256_default_init,
|
|
};
|
|
|
|
static const struct flash_info gigadevice_parts[] = {
|
|
{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
|
|
{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
|
|
SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
|
|
.fixups = &gd25q256_fixups },
|
|
};
|
|
|
|
const struct spi_nor_manufacturer spi_nor_gigadevice = {
|
|
.name = "gigadevice",
|
|
.parts = gigadevice_parts,
|
|
.nparts = ARRAY_SIZE(gigadevice_parts),
|
|
};
|