mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
398ed29225
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
1395 lines
37 KiB
Plaintext
1395 lines
37 KiB
Plaintext
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Eddie Huang <eddie.huang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt8173-larb-port.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/reset/mt8173-resets.h>
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#include <dt-bindings/gce/mt8173-gce.h>
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#include "mt8173-pinfunc.h"
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/ {
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compatible = "mediatek,mt8173";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ovl0 = &ovl0;
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ovl1 = &ovl1;
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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rdma2 = &rdma2;
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wdma0 = &wdma0;
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wdma1 = &wdma1;
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color0 = &color0;
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color1 = &color1;
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split0 = &split0;
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split1 = &split1;
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dpi0 = &dpi0;
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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mdp_rdma0 = &mdp_rdma0;
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mdp_rdma1 = &mdp_rdma1;
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mdp_rsz0 = &mdp_rsz0;
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mdp_rsz1 = &mdp_rsz1;
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mdp_rsz2 = &mdp_rsz2;
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mdp_wdma0 = &mdp_wdma0;
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mdp_wrot0 = &mdp_wrot0;
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mdp_wrot1 = &mdp_wrot1;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <859000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <908000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <983000>;
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};
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opp-1105000000 {
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opp-hz = /bits/ 64 <1105000000>;
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opp-microvolt = <1009000>;
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};
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opp-1209000000 {
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opp-hz = /bits/ 64 <1209000000>;
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opp-microvolt = <1034000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1057000>;
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};
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opp-1508000000 {
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opp-hz = /bits/ 64 <1508000000>;
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opp-microvolt = <1109000>;
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};
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opp-1703000000 {
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opp-hz = /bits/ 64 <1703000000>;
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opp-microvolt = <1125000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <828000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <867000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <927000>;
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};
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opp-1209000000 {
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opp-hz = /bits/ 64 <1209000000>;
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opp-microvolt = <968000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1404000000>;
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opp-microvolt = <1007000>;
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};
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opp-1612000000 {
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opp-hz = /bits/ 64 <1612000000>;
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opp-microvolt = <1049000>;
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};
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opp-1807000000 {
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opp-hz = /bits/ 64 <1807000000>;
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opp-microvolt = <1089000>;
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};
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opp-2106000000 {
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opp-hz = /bits/ 64 <2106000000>;
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opp-microvolt = <1125000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster1_opp>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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entry-latency-us = <639>;
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exit-latency-us = <680>;
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min-residency-us = <1088>;
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arm,psci-suspend-param = <0x0010000>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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clk32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "clk32k";
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};
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cpum_ck: oscillator@2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "cpum_ck";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal>;
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sustainable-power = <1500>; /* milliwatts */
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trips {
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threshold: trip-point@0 {
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temperature = <68000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit@0 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map@0 {
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trip = <&target>;
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cooling-device = <&cpu0 0 0>,
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<&cpu1 0 0>;
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contribution = <3072>;
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};
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map@1 {
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trip = <&target>;
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cooling-device = <&cpu2 0 0>,
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<&cpu3 0 0>;
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contribution = <1024>;
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};
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};
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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vpu_dma_reserved: vpu_dma_mem_region {
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compatible = "shared-dma-pool";
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reg = <0 0xb7000000 0 0x500000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8173-topckgen";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: power-controller@10001000 {
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compatible = "mediatek,mt8173-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: power-controller@10003000 {
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compatible = "mediatek,mt8173-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg_pctl_a@10005000 {
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compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8173-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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hdmi_pin: xxx {
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/*hdmi htplg pin*/
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pins1 {
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pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
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input-enable;
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bias-pull-down;
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};
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};
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i2c0_pins_a: i2c0 {
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pins1 {
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pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
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<MT8173_PIN_46_SCL0__FUNC_SCL0>;
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bias-disable;
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};
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};
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i2c1_pins_a: i2c1 {
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pins1 {
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pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
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<MT8173_PIN_126_SCL1__FUNC_SCL1>;
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bias-disable;
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};
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};
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i2c2_pins_a: i2c2 {
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pins1 {
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pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
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<MT8173_PIN_44_SCL2__FUNC_SCL2>;
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bias-disable;
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};
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};
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i2c3_pins_a: i2c3 {
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pins1 {
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pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
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<MT8173_PIN_107_SCL3__FUNC_SCL3>;
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bias-disable;
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};
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};
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i2c4_pins_a: i2c4 {
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pins1 {
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pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
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<MT8173_PIN_134_SCL4__FUNC_SCL4>;
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bias-disable;
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};
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};
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i2c6_pins_a: i2c6 {
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pins1 {
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pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
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<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
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bias-disable;
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};
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};
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt8173-scpsys";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "mfg", "mm", "venc", "venc_lt";
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infracfg = <&infracfg>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt8173-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt8173-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CLK_13M>,
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<&topckgen CLK_TOP_RTC_SEL>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt8173-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
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clock-names = "spi", "wrap";
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};
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cec: cec@10013000 {
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compatible = "mediatek,mt8173-cec";
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reg = <0 0x10013000 0 0xbc>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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status = "disabled";
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};
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vpu: vpu@10020000 {
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compatible = "mediatek,mt8173-vpu";
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reg = <0 0x10020000 0 0x30000>,
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<0 0x10050000 0 0x100>;
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reg-names = "tcm", "cfg_reg";
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_SCP_SEL>;
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clock-names = "main";
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memory-region = <&vpu_dma_reserved>;
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt8173-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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iommu: iommu@10205000 {
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compatible = "mediatek,mt8173-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2
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&larb3 &larb4 &larb5>;
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#iommu-cells = <1>;
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};
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|
|
efuse: efuse@10206000 {
|
|
compatible = "mediatek,mt8173-efuse";
|
|
reg = <0 0x10206000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
thermal_calibration: calib@528 {
|
|
reg = <0x528 0xc>;
|
|
};
|
|
};
|
|
|
|
apmixedsys: clock-controller@10209000 {
|
|
compatible = "mediatek,mt8173-apmixedsys";
|
|
reg = <0 0x10209000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
hdmi_phy: hdmi-phy@10209100 {
|
|
compatible = "mediatek,mt8173-hdmi-phy";
|
|
reg = <0 0x10209100 0 0x24>;
|
|
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
|
clock-names = "pll_ref";
|
|
clock-output-names = "hdmitx_dig_cts";
|
|
mediatek,ibias = <0xa>;
|
|
mediatek,ibias_up = <0x1c>;
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gce: mailbox@10212000 {
|
|
compatible = "mediatek,mt8173-gce";
|
|
reg = <0 0x10212000 0 0x1000>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg CLK_INFRA_GCE>;
|
|
clock-names = "gce";
|
|
#mbox-cells = <3>;
|
|
};
|
|
|
|
mipi_tx0: mipi-dphy@10215000 {
|
|
compatible = "mediatek,mt8173-mipi-tx";
|
|
reg = <0 0x10215000 0 0x1000>;
|
|
clocks = <&clk26m>;
|
|
clock-output-names = "mipi_tx0_pll";
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi_tx1: mipi-dphy@10216000 {
|
|
compatible = "mediatek,mt8173-mipi-tx";
|
|
reg = <0 0x10216000 0 0x1000>;
|
|
clocks = <&clk26m>;
|
|
clock-output-names = "mipi_tx1_pll";
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@10220000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0 0x10221000 0 0x1000>,
|
|
<0 0x10222000 0 0x2000>,
|
|
<0 0x10224000 0 0x2000>,
|
|
<0 0x10226000 0 0x2000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
auxadc: auxadc@11001000 {
|
|
compatible = "mediatek,mt8173-auxadc";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
clocks = <&pericfg CLK_PERI_AUXADC>;
|
|
clock-names = "main";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,mt8173-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x400>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,mt8173-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x400>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@11004000 {
|
|
compatible = "mediatek,mt8173-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11004000 0 0x400>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@11005000 {
|
|
compatible = "mediatek,mt8173-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11005000 0 0x400>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@11007000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11007000 0 0x70>,
|
|
<0 0x11000100 0 0x80>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C0>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11008000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11008000 0 0x70>,
|
|
<0 0x11000180 0 0x80>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C1>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@11009000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11009000 0 0x70>,
|
|
<0 0x11000200 0 0x80>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C2>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@1100a000 {
|
|
compatible = "mediatek,mt8173-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&pericfg CLK_PERI_SPI0>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal: thermal@1100b000 {
|
|
#thermal-sensor-cells = <0>;
|
|
compatible = "mediatek,mt8173-thermal";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
|
|
clock-names = "therm", "auxadc";
|
|
resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
|
|
mediatek,auxadc = <&auxadc>;
|
|
mediatek,apmixedsys = <&apmixedsys>;
|
|
nvmem-cells = <&thermal_calibration>;
|
|
nvmem-cell-names = "calibration-data";
|
|
};
|
|
|
|
nor_flash: spi@1100d000 {
|
|
compatible = "mediatek,mt8173-nor";
|
|
reg = <0 0x1100d000 0 0xe0>;
|
|
clocks = <&pericfg CLK_PERI_SPI>,
|
|
<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
|
|
clock-names = "spi", "sf";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@11010000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11010000 0 0x70>,
|
|
<0 0x11000280 0 0x80>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C3>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@11011000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11011000 0 0x70>,
|
|
<0 0x11000300 0 0x80>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C4>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmiddc0: i2c@11012000 {
|
|
compatible = "mediatek,mt8173-hdmi-ddc";
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
|
reg = <0 0x11012000 0 0x1C>;
|
|
clocks = <&pericfg CLK_PERI_I2C5>;
|
|
clock-names = "ddc-i2c";
|
|
};
|
|
|
|
i2c6: i2c@11013000 {
|
|
compatible = "mediatek,mt8173-i2c";
|
|
reg = <0 0x11013000 0 0x70>,
|
|
<0 0x11000080 0 0x80>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-div = <16>;
|
|
clocks = <&pericfg CLK_PERI_I2C6>,
|
|
<&pericfg CLK_PERI_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_pins_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
afe: audio-controller@11220000 {
|
|
compatible = "mediatek,mt8173-afe-pcm";
|
|
reg = <0 0x11220000 0 0x1000>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
|
|
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
|
<&topckgen CLK_TOP_AUDIO_SEL>,
|
|
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
|
|
<&topckgen CLK_TOP_APLL1_DIV0>,
|
|
<&topckgen CLK_TOP_APLL2_DIV0>,
|
|
<&topckgen CLK_TOP_I2S0_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S1_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S2_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S3_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S3_B_SEL>;
|
|
clock-names = "infra_sys_audio_clk",
|
|
"top_pdn_audio",
|
|
"top_pdn_aud_intbus",
|
|
"bck0",
|
|
"bck1",
|
|
"i2s0_m",
|
|
"i2s1_m",
|
|
"i2s2_m",
|
|
"i2s3_m",
|
|
"i2s3_b";
|
|
assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
|
|
<&topckgen CLK_TOP_AUD_2_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
|
|
<&topckgen CLK_TOP_APLL2>;
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt8173-mmc";
|
|
reg = <0 0x11230000 0 0x1000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt8173-mmc";
|
|
reg = <0 0x11240000 0 0x1000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
|
<&topckgen CLK_TOP_AXI_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc2: mmc@11250000 {
|
|
compatible = "mediatek,mt8173-mmc";
|
|
reg = <0 0x11250000 0 0x1000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_2>,
|
|
<&topckgen CLK_TOP_AXI_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc3: mmc@11260000 {
|
|
compatible = "mediatek,mt8173-mmc";
|
|
reg = <0 0x11260000 0 0x1000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_3>,
|
|
<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusb: usb@11271000 {
|
|
compatible = "mediatek,mt8173-mtu3";
|
|
reg = <0 0x11271000 0 0x3000>,
|
|
<0 0x11280700 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
|
<&u3port0 PHY_TYPE_USB3>,
|
|
<&u2port1 PHY_TYPE_USB2>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
|
|
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
mediatek,syscon-wakeup = <&pericfg 0x400 1>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usb_host: xhci@11270000 {
|
|
compatible = "mediatek,mt8173-xhci";
|
|
reg = <0 0x11270000 0 0x1000>;
|
|
reg-names = "mac";
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
|
|
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
u3phy: usb-phy@11290000 {
|
|
compatible = "mediatek,mt8173-u3phy";
|
|
reg = <0 0x11290000 0 0x800>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "okay";
|
|
|
|
u2port0: usb-phy@11290800 {
|
|
reg = <0 0x11290800 0 0x100>;
|
|
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port0: usb-phy@11290900 {
|
|
reg = <0 0x11290900 0 0x700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u2port1: usb-phy@11291000 {
|
|
reg = <0 0x11291000 0 0x100>;
|
|
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
mmsys: clock-controller@14000000 {
|
|
compatible = "mediatek,mt8173-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
|
assigned-clock-rates = <400000000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mdp_rdma0: rdma@14001000 {
|
|
compatible = "mediatek,mt8173-mdp-rdma",
|
|
"mediatek,mt8173-mdp";
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
|
|
<&mmsys CLK_MM_MUTEX_32K>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
|
|
mediatek,larb = <&larb0>;
|
|
mediatek,vpu = <&vpu>;
|
|
};
|
|
|
|
mdp_rdma1: rdma@14002000 {
|
|
compatible = "mediatek,mt8173-mdp-rdma";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_RDMA1>,
|
|
<&mmsys CLK_MM_MUTEX_32K>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
mdp_rsz0: rsz@14003000 {
|
|
compatible = "mediatek,mt8173-mdp-rsz";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
};
|
|
|
|
mdp_rsz1: rsz@14004000 {
|
|
compatible = "mediatek,mt8173-mdp-rsz";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
};
|
|
|
|
mdp_rsz2: rsz@14005000 {
|
|
compatible = "mediatek,mt8173-mdp-rsz";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_RSZ2>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
};
|
|
|
|
mdp_wdma0: wdma@14006000 {
|
|
compatible = "mediatek,mt8173-mdp-wdma";
|
|
reg = <0 0x14006000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_WDMA>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
iommus = <&iommu M4U_PORT_MDP_WDMA>;
|
|
mediatek,larb = <&larb0>;
|
|
};
|
|
|
|
mdp_wrot0: wrot@14007000 {
|
|
compatible = "mediatek,mt8173-mdp-wrot";
|
|
reg = <0 0x14007000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
iommus = <&iommu M4U_PORT_MDP_WROT0>;
|
|
mediatek,larb = <&larb0>;
|
|
};
|
|
|
|
mdp_wrot1: wrot@14008000 {
|
|
compatible = "mediatek,mt8173-mdp-wrot";
|
|
reg = <0 0x14008000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_WROT1>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
iommus = <&iommu M4U_PORT_MDP_WROT1>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
ovl0: ovl@1400c000 {
|
|
compatible = "mediatek,mt8173-disp-ovl";
|
|
reg = <0 0x1400c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
|
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
|
mediatek,larb = <&larb0>;
|
|
};
|
|
|
|
ovl1: ovl@1400d000 {
|
|
compatible = "mediatek,mt8173-disp-ovl";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
|
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
rdma0: rdma@1400e000 {
|
|
compatible = "mediatek,mt8173-disp-rdma";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
|
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
|
mediatek,larb = <&larb0>;
|
|
};
|
|
|
|
rdma1: rdma@1400f000 {
|
|
compatible = "mediatek,mt8173-disp-rdma";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
|
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
rdma2: rdma@14010000 {
|
|
compatible = "mediatek,mt8173-disp-rdma";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
|
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
wdma0: wdma@14011000 {
|
|
compatible = "mediatek,mt8173-disp-wdma";
|
|
reg = <0 0x14011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
|
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
|
mediatek,larb = <&larb0>;
|
|
};
|
|
|
|
wdma1: wdma@14012000 {
|
|
compatible = "mediatek,mt8173-disp-wdma";
|
|
reg = <0 0x14012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
|
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
|
mediatek,larb = <&larb4>;
|
|
};
|
|
|
|
color0: color@14013000 {
|
|
compatible = "mediatek,mt8173-disp-color";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
|
};
|
|
|
|
color1: color@14014000 {
|
|
compatible = "mediatek,mt8173-disp-color";
|
|
reg = <0 0x14014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
|
};
|
|
|
|
aal@14015000 {
|
|
compatible = "mediatek,mt8173-disp-aal";
|
|
reg = <0 0x14015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
|
};
|
|
|
|
gamma@14016000 {
|
|
compatible = "mediatek,mt8173-disp-gamma";
|
|
reg = <0 0x14016000 0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
|
};
|
|
|
|
merge@14017000 {
|
|
compatible = "mediatek,mt8173-disp-merge";
|
|
reg = <0 0x14017000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_MERGE>;
|
|
};
|
|
|
|
split0: split@14018000 {
|
|
compatible = "mediatek,mt8173-disp-split";
|
|
reg = <0 0x14018000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
|
};
|
|
|
|
split1: split@14019000 {
|
|
compatible = "mediatek,mt8173-disp-split";
|
|
reg = <0 0x14019000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
|
|
};
|
|
|
|
ufoe@1401a000 {
|
|
compatible = "mediatek,mt8173-disp-ufoe";
|
|
reg = <0 0x1401a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
|
};
|
|
|
|
dsi0: dsi@1401b000 {
|
|
compatible = "mediatek,mt8173-dsi";
|
|
reg = <0 0x1401b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
|
|
<&mmsys CLK_MM_DSI0_DIGITAL>,
|
|
<&mipi_tx0>;
|
|
clock-names = "engine", "digital", "hs";
|
|
phys = <&mipi_tx0>;
|
|
phy-names = "dphy";
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi1: dsi@1401c000 {
|
|
compatible = "mediatek,mt8173-dsi";
|
|
reg = <0 0x1401c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
|
|
<&mmsys CLK_MM_DSI1_DIGITAL>,
|
|
<&mipi_tx1>;
|
|
clock-names = "engine", "digital", "hs";
|
|
phy = <&mipi_tx1>;
|
|
phy-names = "dphy";
|
|
status = "disabled";
|
|
};
|
|
|
|
dpi0: dpi@1401d000 {
|
|
compatible = "mediatek,mt8173-dpi";
|
|
reg = <0 0x1401d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
|
|
<&mmsys CLK_MM_DPI_ENGINE>,
|
|
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
|
clock-names = "pixel", "engine", "pll";
|
|
status = "disabled";
|
|
|
|
port {
|
|
dpi0_out: endpoint {
|
|
remote-endpoint = <&hdmi0_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pwm0: pwm@1401e000 {
|
|
compatible = "mediatek,mt8173-disp-pwm",
|
|
"mediatek,mt6595-disp-pwm";
|
|
reg = <0 0x1401e000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
|
|
<&mmsys CLK_MM_DISP_PWM0MM>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@1401f000 {
|
|
compatible = "mediatek,mt8173-disp-pwm",
|
|
"mediatek,mt6595-disp-pwm";
|
|
reg = <0 0x1401f000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&mmsys CLK_MM_DISP_PWM126M>,
|
|
<&mmsys CLK_MM_DISP_PWM1MM>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
mutex: mutex@14020000 {
|
|
compatible = "mediatek,mt8173-disp-mutex";
|
|
reg = <0 0x14020000 0 0x1000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
|
};
|
|
|
|
larb0: larb@14021000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x14021000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
|
<&mmsys CLK_MM_SMI_LARB0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_common: smi@14022000 {
|
|
compatible = "mediatek,mt8173-smi-common";
|
|
reg = <0 0x14022000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
od@14023000 {
|
|
compatible = "mediatek,mt8173-disp-od";
|
|
reg = <0 0x14023000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_DISP_OD>;
|
|
};
|
|
|
|
hdmi0: hdmi@14025000 {
|
|
compatible = "mediatek,mt8173-hdmi";
|
|
reg = <0 0x14025000 0 0x400>;
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
|
<&mmsys CLK_MM_HDMI_PLLCK>,
|
|
<&mmsys CLK_MM_HDMI_AUDIO>,
|
|
<&mmsys CLK_MM_HDMI_SPDIF>;
|
|
clock-names = "pixel", "pll", "bclk", "spdif";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_pin>;
|
|
phys = <&hdmi_phy>;
|
|
phy-names = "hdmi";
|
|
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
|
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
|
|
assigned-clock-parents = <&hdmi_phy>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
hdmi0_in: endpoint {
|
|
remote-endpoint = <&dpi0_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
larb4: larb@14027000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x14027000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_SMI_LARB4>,
|
|
<&mmsys CLK_MM_SMI_LARB4>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
imgsys: clock-controller@15000000 {
|
|
compatible = "mediatek,mt8173-imgsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb2: larb@15001000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x15001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
|
|
clocks = <&imgsys CLK_IMG_LARB2_SMI>,
|
|
<&imgsys CLK_IMG_LARB2_SMI>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
vdecsys: clock-controller@16000000 {
|
|
compatible = "mediatek,mt8173-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vcodec_dec: vcodec@16000000 {
|
|
compatible = "mediatek,mt8173-vcodec-dec";
|
|
reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
|
|
<0 0x16020000 0 0x1000>, /* VDEC_MISC */
|
|
<0 0x16021000 0 0x800>, /* VDEC_LD */
|
|
<0 0x16021800 0 0x800>, /* VDEC_TOP */
|
|
<0 0x16022000 0 0x1000>, /* VDEC_CM */
|
|
<0 0x16023000 0 0x1000>, /* VDEC_AD */
|
|
<0 0x16024000 0 0x1000>, /* VDEC_AV */
|
|
<0 0x16025000 0 0x1000>, /* VDEC_PP */
|
|
<0 0x16026800 0 0x800>, /* VDEC_HWD */
|
|
<0 0x16027000 0 0x800>, /* VDEC_HWQ */
|
|
<0 0x16027800 0 0x800>, /* VDEC_HWB */
|
|
<0 0x16028400 0 0x400>; /* VDEC_HWG */
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,larb = <&larb1>;
|
|
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
|
|
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
|
|
mediatek,vpu = <&vpu>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
|
|
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D2>,
|
|
<&topckgen CLK_TOP_CCI400_SEL>,
|
|
<&topckgen CLK_TOP_VDEC_SEL>,
|
|
<&topckgen CLK_TOP_VCODECPLL>,
|
|
<&apmixedsys CLK_APMIXED_VENCPLL>,
|
|
<&topckgen CLK_TOP_VENC_LT_SEL>,
|
|
<&topckgen CLK_TOP_VCODECPLL_370P5>;
|
|
clock-names = "vcodecpll",
|
|
"univpll_d2",
|
|
"clk_cci400_sel",
|
|
"vdec_sel",
|
|
"vdecpll",
|
|
"vencpll",
|
|
"venc_lt_sel",
|
|
"vdec_bus_clk_src";
|
|
};
|
|
|
|
larb1: larb@16010000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x16010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
|
|
clocks = <&vdecsys CLK_VDEC_CKEN>,
|
|
<&vdecsys CLK_VDEC_LARB_CKEN>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
vencsys: clock-controller@18000000 {
|
|
compatible = "mediatek,mt8173-vencsys", "syscon";
|
|
reg = <0 0x18000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb3: larb@18001000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x18001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
|
|
clocks = <&vencsys CLK_VENC_CKE1>,
|
|
<&vencsys CLK_VENC_CKE0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
vcodec_enc: vcodec@18002000 {
|
|
compatible = "mediatek,mt8173-vcodec-enc";
|
|
reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
|
|
<0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,larb = <&larb3>,
|
|
<&larb5>;
|
|
iommus = <&iommu M4U_PORT_VENC_RCPU>,
|
|
<&iommu M4U_PORT_VENC_REC>,
|
|
<&iommu M4U_PORT_VENC_BSDMA>,
|
|
<&iommu M4U_PORT_VENC_SV_COMV>,
|
|
<&iommu M4U_PORT_VENC_RD_COMV>,
|
|
<&iommu M4U_PORT_VENC_CUR_LUMA>,
|
|
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
|
|
<&iommu M4U_PORT_VENC_REF_LUMA>,
|
|
<&iommu M4U_PORT_VENC_REF_CHROMA>,
|
|
<&iommu M4U_PORT_VENC_NBM_RDMA>,
|
|
<&iommu M4U_PORT_VENC_NBM_WDMA>,
|
|
<&iommu M4U_PORT_VENC_RCPU_SET2>,
|
|
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
|
|
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
|
|
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
|
|
mediatek,vpu = <&vpu>;
|
|
clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
|
|
<&topckgen CLK_TOP_VENC_SEL>,
|
|
<&topckgen CLK_TOP_UNIVPLL1_D2>,
|
|
<&topckgen CLK_TOP_VENC_LT_SEL>;
|
|
clock-names = "venc_sel_src",
|
|
"venc_sel",
|
|
"venc_lt_sel_src",
|
|
"venc_lt_sel";
|
|
};
|
|
|
|
vencltsys: clock-controller@19000000 {
|
|
compatible = "mediatek,mt8173-vencltsys", "syscon";
|
|
reg = <0 0x19000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb5: larb@19001000 {
|
|
compatible = "mediatek,mt8173-smi-larb";
|
|
reg = <0 0x19001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
|
|
clocks = <&vencltsys CLK_VENCLT_CKE1>,
|
|
<&vencltsys CLK_VENCLT_CKE0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
};
|
|
};
|
|
|