mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-14 08:35:15 +07:00
64d26f8c1d
Add the 0.8GHz and 1GHz opps. According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
714 lines
19 KiB
Plaintext
714 lines
19 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright 2017 NXP
|
|
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
|
*/
|
|
|
|
#include <dt-bindings/clock/imx8mq-clock.h>
|
|
#include <dt-bindings/power/imx8mq-power.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include "imx8mq-pinfunc.h"
|
|
|
|
/ {
|
|
interrupt-parent = <&gpc>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
i2c0 = &i2c1;
|
|
i2c1 = &i2c2;
|
|
i2c2 = &i2c3;
|
|
i2c3 = &i2c4;
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
spi0 = &ecspi1;
|
|
spi1 = &ecspi2;
|
|
spi2 = &ecspi3;
|
|
};
|
|
|
|
ckil: clock-ckil {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "ckil";
|
|
};
|
|
|
|
osc_25m: clock-osc-25m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
clock-output-names = "osc_25m";
|
|
};
|
|
|
|
osc_27m: clock-osc-27m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <27000000>;
|
|
clock-output-names = "osc_27m";
|
|
};
|
|
|
|
clk_ext1: clock-ext1 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <133000000>;
|
|
clock-output-names = "clk_ext1";
|
|
};
|
|
|
|
clk_ext2: clock-ext2 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <133000000>;
|
|
clock-output-names = "clk_ext2";
|
|
};
|
|
|
|
clk_ext3: clock-ext3 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <133000000>;
|
|
clock-output-names = "clk_ext3";
|
|
};
|
|
|
|
clk_ext4: clock-ext4 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency= <133000000>;
|
|
clock-output-names = "clk_ext4";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
A53_0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clk IMX8MQ_CLK_ARM>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&A53_L2>;
|
|
operating-points-v2 = <&a53_opp_table>;
|
|
};
|
|
|
|
A53_1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x1>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clk IMX8MQ_CLK_ARM>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&A53_L2>;
|
|
operating-points-v2 = <&a53_opp_table>;
|
|
};
|
|
|
|
A53_2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x2>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clk IMX8MQ_CLK_ARM>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&A53_L2>;
|
|
operating-points-v2 = <&a53_opp_table>;
|
|
};
|
|
|
|
A53_3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x3>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clk IMX8MQ_CLK_ARM>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&A53_L2>;
|
|
operating-points-v2 = <&a53_opp_table>;
|
|
};
|
|
|
|
A53_L2: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
|
|
interrupt-parent = <&gic>;
|
|
arm,no-tick-in-suspend;
|
|
};
|
|
|
|
soc@0 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x0 0x3e000000>;
|
|
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
|
|
|
|
bus@30000000 { /* AIPS1 */
|
|
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x30000000 0x30000000 0x400000>;
|
|
|
|
gpio1: gpio@30200000 {
|
|
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30200000 0x10000>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@30210000 {
|
|
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30210000 0x10000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@30220000 {
|
|
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30220000 0x10000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@30230000 {
|
|
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30230000 0x10000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@30240000 {
|
|
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30240000 0x10000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
wdog1: watchdog@30280000 {
|
|
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30280000 0x10000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog2: watchdog@30290000 {
|
|
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30290000 0x10000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: watchdog@302a0000 {
|
|
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
|
reg = <0x302a0000 0x10000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc: iomuxc@30330000 {
|
|
compatible = "fsl,imx8mq-iomuxc";
|
|
reg = <0x30330000 0x10000>;
|
|
};
|
|
|
|
iomuxc_gpr: syscon@30340000 {
|
|
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
|
|
reg = <0x30340000 0x10000>;
|
|
};
|
|
|
|
ocotp: ocotp-ctrl@30350000 {
|
|
compatible = "fsl,imx8mq-ocotp", "syscon";
|
|
reg = <0x30350000 0x10000>;
|
|
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
anatop: syscon@30360000 {
|
|
compatible = "fsl,imx8mq-anatop", "syscon";
|
|
reg = <0x30360000 0x10000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
snvs: snvs@30370000 {
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
reg = <0x30370000 0x10000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp{
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap =<&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
};
|
|
|
|
clk: clock-controller@30380000 {
|
|
compatible = "fsl,imx8mq-ccm";
|
|
reg = <0x30380000 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <1>;
|
|
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
|
<&clk_ext1>, <&clk_ext2>,
|
|
<&clk_ext3>, <&clk_ext4>;
|
|
clock-names = "ckil", "osc_25m", "osc_27m",
|
|
"clk_ext1", "clk_ext2",
|
|
"clk_ext3", "clk_ext4";
|
|
};
|
|
|
|
gpc: gpc@303a0000 {
|
|
compatible = "fsl,imx8mq-gpc";
|
|
reg = <0x303a0000 0x10000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
pgc {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pgc_mipi: power-domain@0 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_MIPI>;
|
|
};
|
|
|
|
pgc_pcie1: power-domain@1 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_PCIE1>;
|
|
};
|
|
|
|
pgc_otg1: power-domain@2 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
|
|
};
|
|
|
|
pgc_otg2: power-domain@3 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
|
|
};
|
|
|
|
pgc_ddr1: power-domain@4 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_DDR1>;
|
|
};
|
|
|
|
pgc_gpu: power-domain@5 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_GPU>;
|
|
clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
|
|
<&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
|
|
<&clk IMX8MQ_CLK_GPU_AXI>,
|
|
<&clk IMX8MQ_CLK_GPU_AHB>;
|
|
};
|
|
|
|
pgc_vpu: power-domain@6 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_VPU>;
|
|
};
|
|
|
|
pgc_disp: power-domain@7 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
pgc_mipi_csi1: power-domain@8 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
|
|
};
|
|
|
|
pgc_mipi_csi2: power-domain@9 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
|
|
};
|
|
|
|
pgc_pcie2: power-domain@a {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8M_POWER_DOMAIN_PCIE2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
bus@30400000 { /* AIPS2 */
|
|
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x30400000 0x30400000 0x400000>;
|
|
|
|
pwm1: pwm@30660000 {
|
|
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30660000 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
|
|
<&clk IMX8MQ_CLK_PWM1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@30670000 {
|
|
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30670000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
|
|
<&clk IMX8MQ_CLK_PWM2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@30680000 {
|
|
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30680000 0x10000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
|
|
<&clk IMX8MQ_CLK_PWM3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@30690000 {
|
|
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30690000 0x10000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
|
|
<&clk IMX8MQ_CLK_PWM4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
bus@30800000 { /* AIPS3 */
|
|
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x30800000 0x30800000 0x400000>,
|
|
<0x08000000 0x08000000 0x10000000>;
|
|
|
|
ecspi1: spi@30820000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30820000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
|
|
<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: spi@30830000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30830000 0x10000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
|
|
<&clk IMX8MQ_CLK_ECSPI2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi3: spi@30840000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30840000 0x10000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
|
|
<&clk IMX8MQ_CLK_ECSPI3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@30860000 {
|
|
compatible = "fsl,imx8mq-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30860000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
|
|
<&clk IMX8MQ_CLK_UART1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@30880000 {
|
|
compatible = "fsl,imx8mq-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30880000 0x10000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
|
|
<&clk IMX8MQ_CLK_UART3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@30890000 {
|
|
compatible = "fsl,imx8mq-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30890000 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
|
|
<&clk IMX8MQ_CLK_UART2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@30a20000 {
|
|
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a20000 0x10000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@30a30000 {
|
|
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a30000 0x10000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@30a40000 {
|
|
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a40000 0x10000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@30a50000 {
|
|
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a50000 0x10000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@30a60000 {
|
|
compatible = "fsl,imx8mq-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30a60000 0x10000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
|
|
<&clk IMX8MQ_CLK_UART4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: mmc@30b40000 {
|
|
compatible = "fsl,imx8mq-usdhc",
|
|
"fsl,imx7d-usdhc";
|
|
reg = <0x30b40000 0x10000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
|
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
|
|
assigned-clock-rates = <400000000>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@30b50000 {
|
|
compatible = "fsl,imx8mq-usdhc",
|
|
"fsl,imx7d-usdhc";
|
|
reg = <0x30b50000 0x10000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
|
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi0: spi@30bb0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
|
|
reg = <0x30bb0000 0x10000>,
|
|
<0x08000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
|
|
<&clk IMX8MQ_CLK_QSPI_ROOT>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
fec1: ethernet@30be0000 {
|
|
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
|
reg = <0x30be0000 0x10000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
|
|
<&clk IMX8MQ_CLK_ENET1_ROOT>,
|
|
<&clk IMX8MQ_CLK_ENET_TIMER>,
|
|
<&clk IMX8MQ_CLK_ENET_REF>,
|
|
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues = <3>;
|
|
fsl,num-rx-queues = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb_dwc3_0: usb@38100000 {
|
|
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
|
|
reg = <0x38100000 0x10000>;
|
|
clocks = <&clk IMX8MQ_CLK_USB_BUS>,
|
|
<&clk IMX8MQ_CLK_USB_CORE_REF>,
|
|
<&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
|
|
clock-names = "bus_early", "ref", "suspend";
|
|
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
|
|
<&clk IMX8MQ_CLK_USB_CORE_REF>;
|
|
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
|
|
<&clk IMX8MQ_SYS1_PLL_100M>;
|
|
assigned-clock-rates = <500000000>, <100000000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb3_phy0>, <&usb3_phy0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
power-domains = <&pgc_otg1>;
|
|
usb3-resume-missing-cas;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_phy0: usb-phy@381f0040 {
|
|
compatible = "fsl,imx8mq-usb-phy";
|
|
reg = <0x381f0040 0x40>;
|
|
clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
|
|
clock-names = "phy";
|
|
assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
|
|
assigned-clock-rates = <100000000>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_dwc3_1: usb@38200000 {
|
|
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
|
|
reg = <0x38200000 0x10000>;
|
|
clocks = <&clk IMX8MQ_CLK_USB_BUS>,
|
|
<&clk IMX8MQ_CLK_USB_CORE_REF>,
|
|
<&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
|
|
clock-names = "bus_early", "ref", "suspend";
|
|
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
|
|
<&clk IMX8MQ_CLK_USB_CORE_REF>;
|
|
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
|
|
<&clk IMX8MQ_SYS1_PLL_100M>;
|
|
assigned-clock-rates = <500000000>, <100000000>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb3_phy1>, <&usb3_phy1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
power-domains = <&pgc_otg2>;
|
|
usb3-resume-missing-cas;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_phy1: usb-phy@382f0040 {
|
|
compatible = "fsl,imx8mq-usb-phy";
|
|
reg = <0x382f0040 0x40>;
|
|
clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
|
|
clock-names = "phy";
|
|
assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
|
|
assigned-clock-rates = <100000000>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
a53_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-800000000 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
opp-microvolt = <900000>;
|
|
clock-latency-ns = <150000>;
|
|
};
|
|
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <1000000>;
|
|
clock-latency-ns = <150000>;
|
|
opp-suspend;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@38800000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x38800000 0x10000>, /* GIC Dist */
|
|
<0x38880000 0xc0000>, /* GICR */
|
|
<0x31000000 0x2000>, /* GICC */
|
|
<0x31010000 0x2000>, /* GICV */
|
|
<0x31020000 0x2000>; /* GICH */
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
};
|
|
};
|