mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 03:06:50 +07:00
807b90d0be
* Use the same bit for IDE_HFLAG_CS5520 and IDE_HFLAG_VDMA host flags (both are used only by cs5520 host driver currently). * Add IDE_HFLAG_NO_IO32_BIT host flag and use it instead of ->no_io_32bit ide_hwif_t field. * Add IDE_HFLAG_NO_UNMASK_IRQS host flag, then convert dtc2278 and rz1000 host drivers to use it. There should be no functionality changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
712 lines
18 KiB
C
712 lines
18 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
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*
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* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any later
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* version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
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* Interface and Linux Device Driver" Application Note.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/sysdev.h>
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#include <linux/dma-mapping.h>
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#include "ide-timing.h"
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1xxx.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1xxx_ide.h>
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#define DRV_NAME "au1200-ide"
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#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
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/* enable the burstmode in the dbdma */
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#define IDE_AU1XXX_BURSTMODE 1
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static _auide_hwif auide_hwif;
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static int dbdma_init_done;
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#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
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void auide_insw(unsigned long port, void *addr, u32 count)
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{
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_auide_hwif *ahwif = &auide_hwif;
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chan_tab_t *ctp;
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au1x_ddma_desc_t *dp;
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if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
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DDMA_FLAGS_NOIE)) {
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printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
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return;
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}
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ctp = *((chan_tab_t **)ahwif->rx_chan);
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dp = ctp->cur_ptr;
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while (dp->dscr_cmd0 & DSCR_CMD0_V)
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;
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ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
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}
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void auide_outsw(unsigned long port, void *addr, u32 count)
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{
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_auide_hwif *ahwif = &auide_hwif;
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chan_tab_t *ctp;
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au1x_ddma_desc_t *dp;
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if(!put_source_flags(ahwif->tx_chan, (void*)addr,
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count << 1, DDMA_FLAGS_NOIE)) {
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printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
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return;
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}
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ctp = *((chan_tab_t **)ahwif->tx_chan);
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dp = ctp->cur_ptr;
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while (dp->dscr_cmd0 & DSCR_CMD0_V)
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;
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ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
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}
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#endif
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static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
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/* set pio mode! */
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switch(pio) {
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case 0:
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mem_sttime = SBC_IDE_TIMING(PIO0);
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/* set configuration for RCS2# */
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mem_stcfg |= TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
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break;
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case 1:
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mem_sttime = SBC_IDE_TIMING(PIO1);
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/* set configuration for RCS2# */
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mem_stcfg |= TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
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break;
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case 2:
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mem_sttime = SBC_IDE_TIMING(PIO2);
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/* set configuration for RCS2# */
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mem_stcfg &= ~TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
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break;
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case 3:
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mem_sttime = SBC_IDE_TIMING(PIO3);
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/* set configuration for RCS2# */
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mem_stcfg &= ~TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
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break;
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case 4:
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mem_sttime = SBC_IDE_TIMING(PIO4);
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/* set configuration for RCS2# */
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mem_stcfg &= ~TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
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break;
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}
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au_writel(mem_sttime,MEM_STTIME2);
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au_writel(mem_stcfg,MEM_STCFG2);
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}
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static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
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switch(speed) {
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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case XFER_MW_DMA_2:
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mem_sttime = SBC_IDE_TIMING(MDMA2);
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/* set configuration for RCS2# */
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mem_stcfg &= ~TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
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break;
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case XFER_MW_DMA_1:
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mem_sttime = SBC_IDE_TIMING(MDMA1);
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/* set configuration for RCS2# */
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mem_stcfg &= ~TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
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break;
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case XFER_MW_DMA_0:
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mem_sttime = SBC_IDE_TIMING(MDMA0);
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/* set configuration for RCS2# */
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mem_stcfg |= TS_MASK;
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mem_stcfg &= ~TCSOE_MASK;
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mem_stcfg &= ~TOECS_MASK;
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mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
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break;
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#endif
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}
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au_writel(mem_sttime,MEM_STTIME2);
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au_writel(mem_stcfg,MEM_STCFG2);
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}
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/*
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* Multi-Word DMA + DbDMA functions
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*/
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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static int auide_build_dmatable(ide_drive_t *drive)
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{
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int i, iswrite, count = 0;
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ide_hwif_t *hwif = HWIF(drive);
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struct request *rq = HWGROUP(drive)->rq;
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_auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
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struct scatterlist *sg;
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iswrite = (rq_data_dir(rq) == WRITE);
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/* Save for interrupt context */
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ahwif->drive = drive;
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hwif->sg_nents = i = ide_build_sglist(drive, rq);
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if (!i)
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return 0;
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/* fill the descriptors */
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sg = hwif->sg_table;
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while (i && sg_dma_len(sg)) {
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u32 cur_addr;
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u32 cur_len;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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while (cur_len) {
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u32 flags = DDMA_FLAGS_NOIE;
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unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
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if (++count >= PRD_ENTRIES) {
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printk(KERN_WARNING "%s: DMA table too small\n",
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drive->name);
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goto use_pio_instead;
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}
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/* Lets enable intr for the last descriptor only */
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if (1==i)
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flags = DDMA_FLAGS_IE;
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else
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flags = DDMA_FLAGS_NOIE;
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if (iswrite) {
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if(!put_source_flags(ahwif->tx_chan,
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(void*) sg_virt(sg),
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tc, flags)) {
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printk(KERN_ERR "%s failed %d\n",
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__FUNCTION__, __LINE__);
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}
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} else
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{
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if(!put_dest_flags(ahwif->rx_chan,
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(void*) sg_virt(sg),
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tc, flags)) {
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printk(KERN_ERR "%s failed %d\n",
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__FUNCTION__, __LINE__);
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}
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}
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cur_addr += tc;
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cur_len -= tc;
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}
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sg = sg_next(sg);
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i--;
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}
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if (count)
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return 1;
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use_pio_instead:
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ide_destroy_dmatable(drive);
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return 0; /* revert to PIO for this request */
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}
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static int auide_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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if (hwif->sg_nents) {
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ide_destroy_dmatable(drive);
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hwif->sg_nents = 0;
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}
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return 0;
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}
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static void auide_dma_start(ide_drive_t *drive )
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{
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}
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static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
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{
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/* issue cmd to drive */
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ide_execute_command(drive, command, &ide_dma_intr,
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(2*WAIT_CMD), NULL);
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}
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static int auide_dma_setup(ide_drive_t *drive)
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{
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struct request *rq = HWGROUP(drive)->rq;
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if (!auide_build_dmatable(drive)) {
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ide_map_sg(drive, rq);
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return 1;
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}
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drive->waiting_for_dma = 1;
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return 0;
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}
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static u8 auide_mdma_filter(ide_drive_t *drive)
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{
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/*
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* FIXME: ->white_list and ->black_list are based on completely bogus
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* ->ide_dma_check implementation which didn't set neither the host
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* controller timings nor the device for the desired transfer mode.
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*
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* They should be either removed or 0x00 MWDMA mask should be
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* returned for devices on the ->black_list.
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*/
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if (dbdma_init_done == 0) {
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auide_hwif.white_list = ide_in_drive_list(drive->id,
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dma_white_list);
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auide_hwif.black_list = ide_in_drive_list(drive->id,
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dma_black_list);
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auide_hwif.drive = drive;
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auide_ddma_init(&auide_hwif);
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dbdma_init_done = 1;
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}
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/* Is the drive in our DMA black list? */
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if (auide_hwif.black_list)
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printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
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drive->name, drive->id->model);
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return drive->hwif->mwdma_mask;
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}
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static int auide_dma_test_irq(ide_drive_t *drive)
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{
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if (drive->waiting_for_dma == 0)
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printk(KERN_WARNING "%s: ide_dma_test_irq \
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called while not waiting\n", drive->name);
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/* If dbdma didn't execute the STOP command yet, the
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* active bit is still set
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*/
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drive->waiting_for_dma++;
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if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
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printk(KERN_WARNING "%s: timeout waiting for ddma to \
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complete\n", drive->name);
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return 1;
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}
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udelay(10);
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return 0;
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}
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static void auide_dma_host_set(ide_drive_t *drive, int on)
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{
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}
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static void auide_dma_lost_irq(ide_drive_t *drive)
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{
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printk(KERN_ERR "%s: IRQ lost\n", drive->name);
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}
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static void auide_ddma_tx_callback(int irq, void *param)
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{
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_auide_hwif *ahwif = (_auide_hwif*)param;
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ahwif->drive->waiting_for_dma = 0;
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}
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static void auide_ddma_rx_callback(int irq, void *param)
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{
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_auide_hwif *ahwif = (_auide_hwif*)param;
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ahwif->drive->waiting_for_dma = 0;
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}
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#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
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static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
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{
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dev->dev_id = dev_id;
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dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
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dev->dev_intlevel = 0;
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dev->dev_intpolarity = 0;
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dev->dev_tsize = tsize;
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dev->dev_devwidth = devwidth;
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dev->dev_flags = flags;
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}
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#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
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static void auide_dma_timeout(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
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if (hwif->ide_dma_test_irq(drive))
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return;
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hwif->ide_dma_end(drive);
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}
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static int auide_ddma_init(_auide_hwif *auide) {
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dbdev_tab_t source_dev_tab, target_dev_tab;
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u32 dev_id, tsize, devwidth, flags;
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ide_hwif_t *hwif = auide->hwif;
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dev_id = AU1XXX_ATA_DDMA_REQ;
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if (auide->white_list || auide->black_list) {
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tsize = 8;
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devwidth = 32;
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}
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else {
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tsize = 1;
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devwidth = 16;
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printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
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printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
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}
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#ifdef IDE_AU1XXX_BURSTMODE
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flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
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#else
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flags = DEV_FLAGS_SYNC;
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#endif
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/* setup dev_tab for tx channel */
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auide_init_dbdma_dev( &source_dev_tab,
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dev_id,
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tsize, devwidth, DEV_FLAGS_OUT | flags);
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auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
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auide_init_dbdma_dev( &source_dev_tab,
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dev_id,
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tsize, devwidth, DEV_FLAGS_IN | flags);
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auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
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/* We also need to add a target device for the DMA */
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auide_init_dbdma_dev( &target_dev_tab,
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(u32)DSCR_CMD0_ALWAYS,
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tsize, devwidth, DEV_FLAGS_ANYUSE);
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auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
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/* Get a channel for TX */
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auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
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auide->tx_dev_id,
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auide_ddma_tx_callback,
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(void*)auide);
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/* Get a channel for RX */
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auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
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auide->target_dev_id,
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auide_ddma_rx_callback,
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(void*)auide);
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auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
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NUM_DESCRIPTORS);
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auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
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NUM_DESCRIPTORS);
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hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
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PRD_ENTRIES * PRD_BYTES, /* 1 Page */
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&hwif->dmatable_dma, GFP_KERNEL);
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au1xxx_dbdma_start( auide->tx_chan );
|
|
au1xxx_dbdma_start( auide->rx_chan );
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
|
|
static int auide_ddma_init( _auide_hwif *auide )
|
|
{
|
|
dbdev_tab_t source_dev_tab;
|
|
int flags;
|
|
|
|
#ifdef IDE_AU1XXX_BURSTMODE
|
|
flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
|
|
#else
|
|
flags = DEV_FLAGS_SYNC;
|
|
#endif
|
|
|
|
/* setup dev_tab for tx channel */
|
|
auide_init_dbdma_dev( &source_dev_tab,
|
|
(u32)DSCR_CMD0_ALWAYS,
|
|
8, 32, DEV_FLAGS_OUT | flags);
|
|
auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
|
|
|
|
auide_init_dbdma_dev( &source_dev_tab,
|
|
(u32)DSCR_CMD0_ALWAYS,
|
|
8, 32, DEV_FLAGS_IN | flags);
|
|
auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
|
|
|
|
/* Get a channel for TX */
|
|
auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
|
|
auide->tx_dev_id,
|
|
NULL,
|
|
(void*)auide);
|
|
|
|
/* Get a channel for RX */
|
|
auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
|
|
DSCR_CMD0_ALWAYS,
|
|
NULL,
|
|
(void*)auide);
|
|
|
|
auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
|
|
NUM_DESCRIPTORS);
|
|
auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
|
|
NUM_DESCRIPTORS);
|
|
|
|
au1xxx_dbdma_start( auide->tx_chan );
|
|
au1xxx_dbdma_start( auide->rx_chan );
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
|
|
{
|
|
int i;
|
|
unsigned long *ata_regs = hw->io_ports;
|
|
|
|
/* FIXME? */
|
|
for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
|
|
*ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
|
|
}
|
|
|
|
/* set the Alternative Status register */
|
|
*ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
|
|
}
|
|
|
|
static const struct ide_port_info au1xxx_port_info = {
|
|
.host_flags = IDE_HFLAG_POST_SET_MODE |
|
|
IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
|
|
IDE_HFLAG_NO_IO_32BIT |
|
|
IDE_HFLAG_UNMASK_IRQS,
|
|
.pio_mask = ATA_PIO4,
|
|
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
#endif
|
|
};
|
|
|
|
static int au_ide_probe(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
_auide_hwif *ahwif = &auide_hwif;
|
|
ide_hwif_t *hwif;
|
|
struct resource *res;
|
|
int ret = 0;
|
|
u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
|
|
hw_regs_t hw;
|
|
|
|
#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
|
|
char *mode = "MWDMA2";
|
|
#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
|
|
char *mode = "PIO+DDMA(offload)";
|
|
#endif
|
|
|
|
memset(&auide_hwif, 0, sizeof(_auide_hwif));
|
|
ahwif->irq = platform_get_irq(pdev, 0);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (res == NULL) {
|
|
pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
if (ahwif->irq < 0) {
|
|
pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
|
|
pr_debug("%s: request_mem_region failed\n", DRV_NAME);
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
|
|
if (ahwif->regbase == 0) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
/* FIXME: This might possibly break PCMCIA IDE devices */
|
|
|
|
hwif = &ide_hwifs[pdev->id];
|
|
|
|
memset(&hw, 0, sizeof(hw));
|
|
auide_setup_ports(&hw, ahwif);
|
|
hw.irq = ahwif->irq;
|
|
hw.dev = dev;
|
|
hw.chipset = ide_au1xxx;
|
|
|
|
ide_init_port_hw(hwif, &hw);
|
|
|
|
hwif->dev = dev;
|
|
|
|
/* hold should be on in all cases */
|
|
hwif->hold = 1;
|
|
|
|
hwif->mmio = 1;
|
|
|
|
/* If the user has selected DDMA assisted copies,
|
|
then set up a few local I/O function entry points
|
|
*/
|
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
|
|
hwif->INSW = auide_insw;
|
|
hwif->OUTSW = auide_outsw;
|
|
#endif
|
|
|
|
hwif->set_pio_mode = &au1xxx_set_pio_mode;
|
|
hwif->set_dma_mode = &auide_set_dma_mode;
|
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
|
|
hwif->dma_timeout = &auide_dma_timeout;
|
|
|
|
hwif->mdma_filter = &auide_mdma_filter;
|
|
|
|
hwif->dma_host_set = &auide_dma_host_set;
|
|
hwif->dma_exec_cmd = &auide_dma_exec_cmd;
|
|
hwif->dma_start = &auide_dma_start;
|
|
hwif->ide_dma_end = &auide_dma_end;
|
|
hwif->dma_setup = &auide_dma_setup;
|
|
hwif->ide_dma_test_irq = &auide_dma_test_irq;
|
|
hwif->dma_lost_irq = &auide_dma_lost_irq;
|
|
#endif
|
|
hwif->select_data = 0; /* no chipset-specific code */
|
|
hwif->config_data = 0; /* no chipset-specific code */
|
|
|
|
auide_hwif.hwif = hwif;
|
|
hwif->hwif_data = &auide_hwif;
|
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
|
|
auide_ddma_init(&auide_hwif);
|
|
dbdma_init_done = 1;
|
|
#endif
|
|
|
|
idx[0] = hwif->index;
|
|
|
|
ide_device_add(idx, &au1xxx_port_info);
|
|
|
|
dev_set_drvdata(dev, hwif);
|
|
|
|
printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int au_ide_remove(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct resource *res;
|
|
ide_hwif_t *hwif = dev_get_drvdata(dev);
|
|
_auide_hwif *ahwif = &auide_hwif;
|
|
|
|
ide_unregister(hwif->index, 0, 0);
|
|
|
|
iounmap((void *)ahwif->regbase);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(res->start, res->end - res->start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct device_driver au1200_ide_driver = {
|
|
.name = "au1200-ide",
|
|
.bus = &platform_bus_type,
|
|
.probe = au_ide_probe,
|
|
.remove = au_ide_remove,
|
|
};
|
|
|
|
static int __init au_ide_init(void)
|
|
{
|
|
return driver_register(&au1200_ide_driver);
|
|
}
|
|
|
|
static void __exit au_ide_exit(void)
|
|
{
|
|
driver_unregister(&au1200_ide_driver);
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("AU1200 IDE driver");
|
|
|
|
module_init(au_ide_init);
|
|
module_exit(au_ide_exit);
|