mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b095ae2b9f
There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
12 lines
240 B
ArmAsm
12 lines
240 B
ArmAsm
#include <linux/linkage.h>
|
|
#include <linux/init.h>
|
|
|
|
#include "sleep.h"
|
|
|
|
.section ".text.head", "ax"
|
|
|
|
ENTRY(tegra_secondary_startup)
|
|
bl v7_invalidate_l1
|
|
b secondary_startup
|
|
ENDPROC(tegra_secondary_startup)
|