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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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880d54ff56
This patch reworks the clock binding to avoid too much detail in DT. Now we have only compatible string per type of clock (remark from Rob https://lkml.org/lkml/2016/5/25/492) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
69 lines
1.3 KiB
Plaintext
69 lines
1.3 KiB
Plaintext
Binding for a Clockgen hardware block found on
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certain STMicroelectronics consumer electronics SoC devices.
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A Clockgen node can contain pll, diviser or multiplexer nodes.
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We will find only the base address of the Clockgen, this base
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address is common of all subnode.
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clockgen_node {
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reg = <>;
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pll_node {
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...
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};
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quadfs_node {
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...
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};
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mux_node {
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...
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};
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flexgen_node {
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...
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};
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...
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};
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This binding uses the common clock binding[1].
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Each subnode should use the binding described in [2]..[7]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
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[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
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[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
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Required properties:
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- reg : A Base address and length of the register set.
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Example:
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clockgen-a@090ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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};
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};
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