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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 00:59:39 +07:00
9f37940756
Recent GuC binaries (including all the ones we're currently using) don't require this shared area anymore, having moved the relevant entries into the stage pool instead. i915 itself doesn't write anything into it either, so we can safely drop it. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191031013040.25803-1-daniele.ceraolospurio@intel.com
134 lines
4.8 KiB
C
134 lines
4.8 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#include <linux/types.h>
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struct drm_printer;
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struct drm_i915_private;
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struct i915_gem_context;
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struct i915_request;
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struct intel_context;
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struct intel_engine_cs;
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/* Execlists regs */
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#define RING_ELSP(base) _MMIO((base) + 0x230)
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#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
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#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
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#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8)
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#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
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#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
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#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
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#define EL_CTRL_LOAD (1 << 0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN11_CSB_ENTRIES 12
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#define GEN11_CSB_PTR_MASK 0xf
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#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
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#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
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#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
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#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
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#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
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/* in Gen12 ID 0x7FF is reserved to indicate idle */
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#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
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enum {
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INTEL_CONTEXT_SCHEDULE_IN = 0,
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INTEL_CONTEXT_SCHEDULE_OUT,
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INTEL_CONTEXT_SCHEDULE_PREEMPTED,
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};
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/* Logical Rings */
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int intel_execlists_submission_setup(struct intel_engine_cs *engine);
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int intel_execlists_submission_init(struct intel_engine_cs *engine);
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/* Logical Ring Contexts */
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/* At the start of the context image is its per-process HWS page */
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#define LRC_PPHWSP_PN (0)
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#define LRC_PPHWSP_SZ (1)
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/* After the PPHWSP we have the logical state for the context */
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#define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
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/* Space within PPHWSP reserved to be used as scratch */
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#define LRC_PPHWSP_SCRATCH 0x34
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#define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32))
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void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
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void intel_lr_context_reset(struct intel_engine_cs *engine,
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struct intel_context *ce,
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u32 head,
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bool scrub);
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void intel_execlists_show_requests(struct intel_engine_cs *engine,
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struct drm_printer *m,
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void (*show_request)(struct drm_printer *m,
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struct i915_request *rq,
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const char *prefix),
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unsigned int max);
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struct intel_context *
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intel_execlists_create_virtual(struct i915_gem_context *ctx,
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struct intel_engine_cs **siblings,
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unsigned int count);
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struct intel_context *
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intel_execlists_clone_virtual(struct i915_gem_context *ctx,
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struct intel_engine_cs *src);
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int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
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const struct intel_engine_cs *master,
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const struct intel_engine_cs *sibling);
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struct intel_engine_cs *
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intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
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unsigned int sibling);
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bool
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intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);
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#endif /* _INTEL_LRC_H_ */
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