mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
1edb9ca69e
This patch adds support for Samsung 10Gb ethernet driver(sxgbe). - sxgbe core initialization - Tx and Rx support - MDIO support - ISRs for Tx and Rx - ifconfig support to driver Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Vipul Pandya <vipul.pandya@samsung.com> Signed-off-by: Girish K S <ks.giri@samsung.com> Neatening-by: Joe Perches <joe@perches.com> Signed-off-by: Byungho An <bh74.an@samsung.com> Signed-off-by: David S. Miller <davem@davemloft.net>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include "sxgbe_common.h"
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#include "sxgbe_xpcs.h"
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static int sxgbe_xpcs_read(struct net_device *ndev, unsigned int reg)
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{
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u32 value;
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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value = readl(priv->ioaddr + XPCS_OFFSET + reg);
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return value;
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}
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static int sxgbe_xpcs_write(struct net_device *ndev, int reg, int data)
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{
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struct sxgbe_priv_data *priv = netdev_priv(ndev);
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writel(data, priv->ioaddr + XPCS_OFFSET + reg);
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return 0;
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}
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int sxgbe_xpcs_init(struct net_device *ndev)
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{
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u32 value;
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value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
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/* 10G XAUI mode */
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sxgbe_xpcs_write(ndev, SR_PCS_CONTROL2, XPCS_TYPE_SEL_X);
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sxgbe_xpcs_write(ndev, VR_PCS_MMD_XAUI_MODE_CONTROL, XPCS_XAUI_MODE);
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sxgbe_xpcs_write(ndev, VR_PCS_MMD_XAUI_MODE_CONTROL, value | BIT(13));
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sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value | BIT(11));
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do {
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value = sxgbe_xpcs_read(ndev, VR_PCS_MMD_DIGITAL_STATUS);
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} while ((value & XPCS_QSEQ_STATE_MPLLOFF) == XPCS_QSEQ_STATE_STABLE);
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value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
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sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value & ~BIT(11));
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do {
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value = sxgbe_xpcs_read(ndev, VR_PCS_MMD_DIGITAL_STATUS);
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} while ((value & XPCS_QSEQ_STATE_MPLLOFF) != XPCS_QSEQ_STATE_STABLE);
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return 0;
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}
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int sxgbe_xpcs_init_1G(struct net_device *ndev)
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{
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int value;
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/* 10GBASE-X PCS (1G) mode */
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sxgbe_xpcs_write(ndev, SR_PCS_CONTROL2, XPCS_TYPE_SEL_X);
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sxgbe_xpcs_write(ndev, VR_PCS_MMD_XAUI_MODE_CONTROL, XPCS_XAUI_MODE);
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value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
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sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value & ~BIT(13));
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value = sxgbe_xpcs_read(ndev, SR_MII_MMD_CONTROL);
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sxgbe_xpcs_write(ndev, SR_MII_MMD_CONTROL, value | BIT(6));
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sxgbe_xpcs_write(ndev, SR_MII_MMD_CONTROL, value & ~BIT(13));
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value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
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sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value | BIT(11));
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do {
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value = sxgbe_xpcs_read(ndev, VR_PCS_MMD_DIGITAL_STATUS);
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} while ((value & XPCS_QSEQ_STATE_MPLLOFF) != XPCS_QSEQ_STATE_STABLE);
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value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
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sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value & ~BIT(11));
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/* Auto Negotiation cluase 37 enable */
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value = sxgbe_xpcs_read(ndev, SR_MII_MMD_CONTROL);
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sxgbe_xpcs_write(ndev, SR_MII_MMD_CONTROL, value | BIT(12));
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return 0;
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}
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