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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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50261151a1
The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
111 lines
3.2 KiB
C
111 lines
3.2 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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/*
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* GPU scratch registers helpers function.
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*/
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/**
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* amdgpu_gfx_scratch_get - Allocate a scratch register
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*
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* @adev: amdgpu_device pointer
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* @reg: scratch register mmio offset
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*
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* Allocate a CP scratch register for use by the driver (all asics).
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* Returns 0 on success or -EINVAL on failure.
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*/
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int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
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{
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int i;
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i = ffs(adev->gfx.scratch.free_mask);
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if (i != 0 && i <= adev->gfx.scratch.num_reg) {
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i--;
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adev->gfx.scratch.free_mask &= ~(1u << i);
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*reg = adev->gfx.scratch.reg_base + i;
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return 0;
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}
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return -EINVAL;
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}
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/**
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* amdgpu_gfx_scratch_free - Free a scratch register
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*
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* @adev: amdgpu_device pointer
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* @reg: scratch register mmio offset
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*
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* Free a CP scratch register allocated for use by the driver (all asics)
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*/
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void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
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{
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adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
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}
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/**
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* amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
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*
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* @mask: array in which the per-shader array disable masks will be stored
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* @max_se: number of SEs
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* @max_sh: number of SHs
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*
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* The bitmask of CUs to be disabled in the shader array determined by se and
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* sh is stored in mask[se * max_sh + sh].
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*/
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void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
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{
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unsigned se, sh, cu;
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const char *p;
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memset(mask, 0, sizeof(*mask) * max_se * max_sh);
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if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
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return;
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p = amdgpu_disable_cu;
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for (;;) {
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char *next;
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int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
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if (ret < 3) {
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DRM_ERROR("amdgpu: could not parse disable_cu\n");
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return;
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}
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if (se < max_se && sh < max_sh && cu < 16) {
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DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
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mask[se * max_sh + sh] |= 1u << cu;
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} else {
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DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
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se, sh, cu);
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}
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next = strchr(p, ',');
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if (!next)
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break;
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p = next + 1;
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}
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}
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