mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 14:40:55 +07:00
9693a85378
This patch adds trivial support for SMARTMIPS extension. This extension is currently implemented by 4KS[CD] CPUs. Basically it saves/restores ACX register, which is part of the SMARTMIPS ASE, when needed. This patch does *not* add any support for Smartmips MMU features. Futhermore this patch does not add explicit support for 4KS[CD] CPUs since they are respectively mips32 and mips32r2 compliant. So with the current processor configuration, a platform that has such CPUs needs to select both configs: CPU_HAS_SMARTMIPS SYS_HAS_CPU_MIPS32_R[12] This is due to the processor configuration which is mixing up all the architecture variants and the processor types. The drawback of this, is that we currently pass '-march=mips32' option to gcc when building a kernel instead of '-march=4ksc' for 4KSC case. This can lead to a kernel image a little bit bigger than required. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
|
|
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
|
*/
|
|
#ifndef _ASM_PTRACE_H
|
|
#define _ASM_PTRACE_H
|
|
|
|
|
|
/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
|
|
#define FPR_BASE 32
|
|
#define PC 64
|
|
#define CAUSE 65
|
|
#define BADVADDR 66
|
|
#define MMHI 67
|
|
#define MMLO 68
|
|
#define FPC_CSR 69
|
|
#define FPC_EIR 70
|
|
#define DSP_BASE 71 /* 3 more hi / lo register pairs */
|
|
#define DSP_CONTROL 77
|
|
#define ACX 78
|
|
|
|
/*
|
|
* This struct defines the way the registers are stored on the stack during a
|
|
* system call/exception. As usual the registers k0/k1 aren't being saved.
|
|
*/
|
|
struct pt_regs {
|
|
#ifdef CONFIG_32BIT
|
|
/* Pad bytes for argument save space on the stack. */
|
|
unsigned long pad0[6];
|
|
#endif
|
|
|
|
/* Saved main processor registers. */
|
|
unsigned long regs[32];
|
|
|
|
/* Saved special registers. */
|
|
unsigned long cp0_status;
|
|
unsigned long hi;
|
|
unsigned long lo;
|
|
#ifdef CONFIG_CPU_HAS_SMARTMIPS
|
|
unsigned long acx;
|
|
#endif
|
|
unsigned long cp0_badvaddr;
|
|
unsigned long cp0_cause;
|
|
unsigned long cp0_epc;
|
|
#ifdef CONFIG_MIPS_MT_SMTC
|
|
unsigned long cp0_tcstatus;
|
|
#endif /* CONFIG_MIPS_MT_SMTC */
|
|
} __attribute__ ((aligned (8)));
|
|
|
|
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
|
|
#define PTRACE_GETREGS 12
|
|
#define PTRACE_SETREGS 13
|
|
#define PTRACE_GETFPREGS 14
|
|
#define PTRACE_SETFPREGS 15
|
|
/* #define PTRACE_GETFPXREGS 18 */
|
|
/* #define PTRACE_SETFPXREGS 19 */
|
|
|
|
#define PTRACE_OLDSETOPTIONS 21
|
|
|
|
#define PTRACE_GET_THREAD_AREA 25
|
|
#define PTRACE_SET_THREAD_AREA 26
|
|
|
|
/* Calls to trace a 64bit program from a 32bit program. */
|
|
#define PTRACE_PEEKTEXT_3264 0xc0
|
|
#define PTRACE_PEEKDATA_3264 0xc1
|
|
#define PTRACE_POKETEXT_3264 0xc2
|
|
#define PTRACE_POKEDATA_3264 0xc3
|
|
#define PTRACE_GET_THREAD_AREA_3264 0xc4
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
#include <linux/linkage.h>
|
|
#include <asm/isadep.h>
|
|
|
|
/*
|
|
* Does the process account for user or for system time?
|
|
*/
|
|
#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
|
|
|
|
#define instruction_pointer(regs) ((regs)->cp0_epc)
|
|
#define profile_pc(regs) instruction_pointer(regs)
|
|
|
|
extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
|
|
|
|
extern NORET_TYPE void die(const char *, struct pt_regs *);
|
|
|
|
static inline void die_if_kernel(const char *str, struct pt_regs *regs)
|
|
{
|
|
if (unlikely(!user_mode(regs)))
|
|
die(str, regs);
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* _ASM_PTRACE_H */
|