mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 11:16:48 +07:00
8f3093b348
This adds the Gemini ethernet node to the Gemini SoC. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
416 lines
11 KiB
Plaintext
416 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for Cortina systems Gemini SoC
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/cortina,gemini-clock.h>
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#include <dt-bindings/reset/cortina,gemini-reset.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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flash@30000000 {
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compatible = "cortina,gemini-flash", "cfi-flash";
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syscon = <&syscon>;
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pinctrl-names = "default";
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pinctrl-0 = <&pflash_default_pins>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon",
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"syscon", "simple-mfd";
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reg = <0x40000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&syscon>;
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/* GLOBAL_RESET register */
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offset = <0x0c>;
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/* RESET_GLOBAL | RESET_CPU1 */
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mask = <0xC0000000>;
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};
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pinctrl {
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compatible = "cortina,gemini-pinctrl";
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regmap = <&syscon>;
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/* Hog the DRAM pins */
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pinctrl-names = "default";
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pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
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<&vcontrol_default_pins>;
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dram_default_pins: pinctrl-dram {
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mux {
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function = "dram";
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groups = "dramgrp";
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};
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};
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rtc_default_pins: pinctrl-rtc {
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mux {
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function = "rtc";
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groups = "rtcgrp";
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};
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};
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power_default_pins: pinctrl-power {
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mux {
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function = "power";
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groups = "powergrp";
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};
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};
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cir_default_pins: pinctrl-cir {
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mux {
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function = "cir";
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groups = "cirgrp";
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};
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};
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system_default_pins: pinctrl-system {
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mux {
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function = "system";
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groups = "systemgrp";
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};
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};
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vcontrol_default_pins: pinctrl-vcontrol {
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mux {
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function = "vcontrol";
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groups = "vcontrolgrp";
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};
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};
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ice_default_pins: pinctrl-ice {
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mux {
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function = "ice";
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groups = "icegrp";
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};
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};
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uart_default_pins: pinctrl-uart {
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mux {
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function = "uart";
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groups = "uartrxtxgrp";
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};
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};
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pflash_default_pins: pinctrl-pflash {
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mux {
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function = "pflash";
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groups = "pflashgrp";
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};
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};
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usb_default_pins: pinctrl-usb {
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mux {
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function = "usb";
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groups = "usbgrp";
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};
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};
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gmii_default_pins: pinctrl-gmii {
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/*
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* Only activate GMAC0 by default since
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* GMAC1 will overlap with 8 GPIO lines
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* gpio2a, gpio2b. Overlay groups with
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* "gmii_gmac0_grp", "gmii_gmac1_grp" for
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* both ethernet interfaces.
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*/
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp";
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};
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};
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pci_default_pins: pinctrl-pci {
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mux {
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function = "pci";
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groups = "pcigrp";
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};
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};
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sata_default_pins: pinctrl-sata {
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mux {
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function = "sata";
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groups = "satagrp";
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};
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};
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/* Activate both groups of pins for this state */
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sata_and_ide_pins: pinctrl-sata-ide {
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mux0 {
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function = "sata";
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groups = "satagrp";
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};
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mux1 {
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function = "ide";
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groups = "idegrp";
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};
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};
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tvc_default_pins: pinctrl-tvc {
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mux {
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function = "tvc";
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groups = "tvcgrp";
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};
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};
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};
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};
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watchdog@41000000 {
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compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
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reg = <0x41000000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_WDOG>;
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clocks = <&syscon GEMINI_CLK_APB>;
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clock-names = "PCLK";
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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resets = <&syscon GEMINI_RESET_UART>;
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clocks = <&syscon GEMINI_CLK_UART>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart_default_pins>;
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reg-shift = <2>;
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};
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timer@43000000 {
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compatible = "faraday,fttmr010";
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reg = <0x43000000 0x1000>;
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interrupt-parent = <&intcon>;
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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resets = <&syscon GEMINI_RESET_TIMER>;
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/* APB clock or RTC clock */
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clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
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clock-names = "PCLK", "EXTCLK";
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syscon = <&syscon>;
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};
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rtc@45000000 {
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compatible = "cortina,gemini-rtc";
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reg = <0x45000000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_RTC>;
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clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
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clock-names = "PCLK", "EXTCLK";
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pinctrl-names = "default";
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pinctrl-0 = <&rtc_default_pins>;
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};
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sata: sata@46000000 {
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compatible = "cortina,gemini-sata-bridge";
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reg = <0x46000000 0x100>;
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resets = <&syscon GEMINI_RESET_SATA0>,
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<&syscon GEMINI_RESET_SATA1>;
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reset-names = "sata0", "sata1";
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clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
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<&syscon GEMINI_CLK_GATE_SATA1>;
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clock-names = "SATA0_PCLK", "SATA1_PCLK";
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/*
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* This defines the special "ide" state that needs
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* to be explicitly enabled to enable the IDE pins,
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* as these pins are normally used for other things.
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*/
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pinctrl-names = "default", "ide";
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pinctrl-0 = <&sata_default_pins>;
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pinctrl-1 = <&sata_and_ide_pins>;
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syscon = <&syscon>;
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status = "disabled";
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};
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intcon: interrupt-controller@48000000 {
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compatible = "faraday,ftintc010";
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reg = <0x48000000 0x1000>;
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resets = <&syscon GEMINI_RESET_INTCON0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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power-controller@4b000000 {
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compatible = "cortina,gemini-power-controller";
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reg = <0x4b000000 0x100>;
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interrupts = <26 IRQ_TYPE_EDGE_RISING>;
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pinctrl-names = "default";
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pinctrl-0 = <&power_default_pins>;
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};
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gpio0: gpio@4d000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4d000000 0x100>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GPIO0>;
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clocks = <&syscon GEMINI_CLK_APB>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@4e000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4e000000 0x100>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GPIO1>;
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clocks = <&syscon GEMINI_CLK_APB>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@4f000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4f000000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GPIO2>;
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clocks = <&syscon GEMINI_CLK_APB>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pci@50000000 {
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compatible = "cortina,gemini-pci", "faraday,ftpci100";
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/*
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* The first 256 bytes in the IO range is actually used
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* to configure the host bridge.
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*/
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reg = <0x50000000 0x100>;
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resets = <&syscon GEMINI_RESET_PCI>;
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clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
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clock-names = "PCLK", "PCICLK";
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pinctrl-names = "default";
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pinctrl-0 = <&pci_default_pins>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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status = "disabled";
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bus-range = <0x00 0xff>;
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/* PCI ranges mappings */
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ranges =
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/* 1MiB I/O space 0x50000000-0x500fffff */
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<0x01000000 0 0 0x50000000 0 0x00100000>,
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/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
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<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
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/* DMA ranges */
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dma-ranges =
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/* 128MiB at 0x00000000-0x07ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
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/* 64MiB at 0x00000000-0x03ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
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/* 64MiB at 0x00000000-0x03ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
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/*
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* This PCI host bridge variant has a cascaded interrupt
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* controller embedded in the host bridge.
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*/
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pci_intc: interrupt-controller {
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interrupt-parent = <&intcon>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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ethernet@60000000 {
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compatible = "cortina,gemini-ethernet";
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reg = <0x60000000 0x4000>, /* Global registers, queue */
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<0x60004000 0x2000>, /* V-bit */
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<0x60006000 0x2000>; /* A-bit */
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pinctrl-names = "default";
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pinctrl-0 = <&gmii_default_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gmac0: ethernet-port@0 {
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compatible = "cortina,gemini-ethernet-port";
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reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
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<0x6000a000 0x2000>; /* Port 0 GMAC */
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interrupt-parent = <&intcon>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GMAC0>;
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clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
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clock-names = "PCLK";
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};
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gmac1: ethernet-port@1 {
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compatible = "cortina,gemini-ethernet-port";
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reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
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<0x6000e000 0x2000>; /* Port 1 GMAC */
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interrupt-parent = <&intcon>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GMAC1>;
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clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
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clock-names = "PCLK";
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};
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};
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ata@63000000 {
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compatible = "cortina,gemini-pata", "faraday,ftide010";
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reg = <0x63000000 0x1000>;
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interrupts = <4 IRQ_TYPE_EDGE_RISING>;
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resets = <&syscon GEMINI_RESET_IDE>;
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clocks = <&syscon GEMINI_CLK_GATE_IDE>;
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clock-names = "PCLK";
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sata = <&sata>;
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status = "disabled";
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};
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ata@63400000 {
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compatible = "cortina,gemini-pata", "faraday,ftide010";
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reg = <0x63400000 0x1000>;
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interrupts = <5 IRQ_TYPE_EDGE_RISING>;
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resets = <&syscon GEMINI_RESET_IDE>;
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clocks = <&syscon GEMINI_CLK_GATE_IDE>;
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clock-names = "PCLK";
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sata = <&sata>;
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status = "disabled";
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};
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dma-controller@67000000 {
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compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
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/* Faraday Technology FTDMAC020 variant */
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arm,primecell-periphid = <0x0003b080>;
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reg = <0x67000000 0x1000>;
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interrupts = <9 IRQ_TYPE_EDGE_RISING>;
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resets = <&syscon GEMINI_RESET_DMAC>;
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clocks = <&syscon GEMINI_CLK_AHB>;
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clock-names = "apb_pclk";
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/* Bus interface AHB1 (AHB0) is totally tilted */
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lli-bus-interface-ahb2;
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mem-bus-interface-ahb2;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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#dma-cells = <2>;
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};
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display-controller@6a000000 {
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compatible = "cortina,gemini-tvc", "faraday,tve200";
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reg = <0x6a000000 0x1000>;
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interrupts = <13 IRQ_TYPE_EDGE_RISING>;
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resets = <&syscon GEMINI_RESET_TVC>;
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clocks = <&syscon GEMINI_CLK_GATE_TVC>,
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<&syscon GEMINI_CLK_TVC>;
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clock-names = "PCLK", "TVE";
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pinctrl-names = "default";
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pinctrl-0 = <&tvc_default_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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