mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 11:26:54 +07:00
ca36855ef0
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
145 lines
2.7 KiB
Plaintext
145 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree file for Marvell RD-AXPWiFiAP.
|
|
*
|
|
* Note: this board is shipped with a new generation boot loader that
|
|
* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
|
|
* is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
|
|
* CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
|
|
*
|
|
* Copyright (C) 2013 Marvell
|
|
*
|
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
#include "armada-xp-mv78230.dtsi"
|
|
|
|
/ {
|
|
model = "Marvell RD-AXPWiFiAP";
|
|
compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
|
|
};
|
|
|
|
soc {
|
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
|
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
|
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
|
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
|
|
|
internal-regs {
|
|
/* UART0 */
|
|
serial@12000 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* UART1 */
|
|
serial@12100 {
|
|
status = "okay";
|
|
};
|
|
|
|
sata@a0000 {
|
|
nr-ports = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
ethernet@70000 {
|
|
pinctrl-0 = <&ge0_rgmii_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
phy = <&phy0>;
|
|
phy-mode = "rgmii-id";
|
|
};
|
|
ethernet@74000 {
|
|
pinctrl-0 = <&ge1_rgmii_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
phy = <&phy1>;
|
|
phy-mode = "rgmii-id";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio_keys {
|
|
compatible = "gpio-keys";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-0 = <&keys_pin>;
|
|
pinctrl-names = "default";
|
|
|
|
reset {
|
|
label = "Factory Reset Button";
|
|
linux,code = <KEY_SETUP>;
|
|
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mdio {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
phy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
&pciec {
|
|
status = "okay";
|
|
|
|
/* First mini-PCIe port */
|
|
pcie@1,0 {
|
|
/* Port 0, Lane 0 */
|
|
status = "okay";
|
|
};
|
|
|
|
/* Second mini-PCIe port */
|
|
pcie@2,0 {
|
|
/* Port 0, Lane 1 */
|
|
status = "okay";
|
|
};
|
|
|
|
/* Renesas uPD720202 USB 3.0 controller */
|
|
pcie@3,0 {
|
|
/* Port 0, Lane 3 */
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
pinctrl-0 = <&phy_int_pin>;
|
|
pinctrl-names = "default";
|
|
|
|
keys_pin: keys-pin {
|
|
marvell,pins = "mpp33";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
phy_int_pin: phy-int-pin {
|
|
marvell,pins = "mpp32";
|
|
marvell,function = "gpio";
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
spi-flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "n25q128a13", "jedec,spi-nor";
|
|
reg = <0>; /* Chip select 0 */
|
|
spi-max-frequency = <108000000>;
|
|
};
|
|
};
|