Shay Agroskin 64109f1dc4 net/mlx5e: Replace PTP clock lock from RW lock to seq lock ... Changed "priv.clock.lock" lock from 'rw_lock' to 'seq_lock' in order to improve packet rate performance. Tested on Intel(R) Xeon(R) CPU E5-2660 v2 @ 2.20GHz. Sent 64b packets between two peers connected by ConnectX-5, and measured packet rate for the receiver in three modes: no time-stamping (base rate) time-stamping using rw_lock (old lock) for critical region time-stamping using seq_lock (new lock) for critical region Only the receiver time stamped its packets. The measured packet rate improvements are: Single flow (multiple TX rings to single RX ring): without timestamping: 4.26 (M packets)/sec with rw-lock (old lock): 4.1 (M packets)/sec with seq-lock (new lock): 4.16 (M packets)/sec 1.46% improvement Multiple flows (multiple TX rings to six RX rings): without timestamping: 22 (M packets)/sec with rw-lock (old lock): 11.7 (M packets)/sec with seq-lock (new lock): 21.3 (M packets)/sec 82.05% improvement The packet rate improvement is due to the lack of atomic operations for the 'readers' by the seq-lock. Since there are much more 'readers' than 'writers' contention on this lock, almost all atomic operations are saved. this results in a dramatic decrease in overall cache misses. Signed-off-by: Shay Agroskin <shayag@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>		2018-09-05 21:14:57 -07:00
..
mlx4	net/mlx4/en_rx: Mark expected switch fall-throughs	2018-08-07 17:54:20 -07:00
mlx5/core	net/mlx5e: Replace PTP clock lock from RW lock to seq lock	2018-09-05 21:14:57 -07:00
mlxfw
mlxsw	mlxsw: spectrum_switchdev: Do not leak RIFs when removing bridge	2018-08-25 16:28:20 -07:00
Kconfig
Makefile