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eb7c825bf7
This tag contains fixes, defconfig, and DT data changes for the v5.2-rc
series. The fixes are relatively straightforward:
- Addition of a TLB fence in the vmalloc_fault path, so the CPU doesn't
enter an infinite page fault loop;
- Readdition of the pm_power_off export, so device drivers that
reassign it can now be built as modules;
- A udelay() fix for RV32, fixing a miscomputation of the delay time;
- Removal of deprecated smp_mb__*() barriers.
The tag also adds initial DT data infrastructure for arch/riscv, along
with initial data for the SiFive FU540-C000 SoC and the corresponding
HiFive Unleashed board.
We also update the RV64 defconfig to include some core drivers for the
FU540 in the build.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl0HtEkACgkQx4+xDQu9
KkuRIw//f2vSrUyMh44sevr6euVD0K++hQ0AbteQ94cGHqYWWaNxfwMHFD91Gxbj
wowTwgssq7H9nePsKANjiiLULnZNIkWXAlIncjzv3aXkH6JG3f9nEGR49yzvCbIZ
yN8wgElJ8rcVWLd096E53Su84CzxuJJ2o3wOI1nQi8aI4h3LwkM2b/O4GxZFpnWb
vIhWXqjvbUb8XL7Y+VPewtxnZItOUDHkuIkup4kP2bTgl2iDW93hzWwxNKbt6v+m
9wTzAChjcepCAXSmEGeeZ/h2HNqw2crs+NWOe0drcKxL2vKPZ6gS8ZRX/NuIoDr4
JgMILzYSO28z8N6w1cJJUdN4eGhCTvdxVTQXvkk/yZoT08X6M0xb5A1MbtizgOJ6
mZK/vM9gtuoUSZG0SRNeNoqHbWu1tIm29z435Be8hWAtzXlEfewJm8ntgFO4dGmb
E8TRSgjLzdHY0Nvwx/KVtvYmE/TMybVVRsxJJ525dqJlHT7f3VuRstvw7VQJQpz2
+JfsZbYk1KjbUc25QpAqF1LUxrRQFn2JL0Cqw+L49J8eshY77rsTcAKP6ZZWiSFZ
qodU0oPF4BkS1t0bnFuNwlqsAr/q9EiAnQO7+SvqQY/ZUnMNk9gCNn5k/rHMCfyD
2Dyo6iAbj+Yyb1rrQxX6QnlbHgpFxsG3N4s9E5jOPgKyEQM4JQ4=
=aotJ
-----END PGP SIGNATURE-----
Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
"This contains fixes, defconfig, and DT data changes for the v5.2-rc
series.
The fixes are relatively straightforward:
- Addition of a TLB fence in the vmalloc_fault path, so the CPU
doesn't enter an infinite page fault loop
- Readdition of the pm_power_off export, so device drivers that
reassign it can now be built as modules
- A udelay() fix for RV32, fixing a miscomputation of the delay time
- Removal of deprecated smp_mb__*() barriers
This also adds initial DT data infrastructure for arch/riscv, along
with initial data for the SiFive FU540-C000 SoC and the corresponding
HiFive Unleashed board.
We also update the RV64 defconfig to include some core drivers for the
FU540 in the build"
* tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: remove unused barrier defines
riscv: mm: synchronize MMU after pte change
riscv: dts: add initial board data for the SiFive HiFive Unleashed
riscv: dts: add initial support for the SiFive FU540-C000 SoC
dt-bindings: riscv: convert cpu binding to json-schema
dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
arch: riscv: add support for building DTB files from DT source data
riscv: Fix udelay in RV32.
riscv: export pm_power_off again
RISC-V: defconfig: enable clocks, serial console
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <linux/delay.h>
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#include <linux/param.h>
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#include <linux/timex.h>
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#include <linux/export.h>
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/*
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* This is copies from arch/arm/include/asm/delay.h
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*
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* Loop (or tick) based delay:
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*
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* loops = loops_per_jiffy * jiffies_per_sec * delay_us / us_per_sec
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*
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* where:
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*
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* jiffies_per_sec = HZ
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* us_per_sec = 1000000
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*
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* Therefore the constant part is HZ / 1000000 which is a small
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* fractional number. To make this usable with integer math, we
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* scale up this constant by 2^31, perform the actual multiplication,
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* and scale the result back down by 2^31 with a simple shift:
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*
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* loops = (loops_per_jiffy * delay_us * UDELAY_MULT) >> 31
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*
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* where:
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*
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* UDELAY_MULT = 2^31 * HZ / 1000000
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* = (2^31 / 1000000) * HZ
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* = 2147.483648 * HZ
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* = 2147 * HZ + 483648 * HZ / 1000000
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*
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* 31 is the biggest scale shift value that won't overflow 32 bits for
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* delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000.
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*/
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#define MAX_UDELAY_US 2000
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#define MAX_UDELAY_HZ 1000
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#define UDELAY_MULT (2147UL * HZ + 483648UL * HZ / 1000000UL)
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#define UDELAY_SHIFT 31
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#if HZ > MAX_UDELAY_HZ
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#error "HZ > MAX_UDELAY_HZ"
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#endif
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/*
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* RISC-V supports both UDELAY and NDELAY. This is largely the same as above,
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* but with different constants. I added 10 bits to the shift to get this, but
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* the result is that I need a 64-bit multiply, which is slow on 32-bit
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* platforms.
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*
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* NDELAY_MULT = 2^41 * HZ / 1000000000
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* = (2^41 / 1000000000) * HZ
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* = 2199.02325555 * HZ
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* = 2199 * HZ + 23255550 * HZ / 1000000000
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*
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* The maximum here is to avoid 64-bit overflow, but it isn't checked as it
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* won't happen.
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*/
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#define MAX_NDELAY_NS (1ULL << 42)
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#define MAX_NDELAY_HZ MAX_UDELAY_HZ
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#define NDELAY_MULT ((unsigned long long)(2199ULL * HZ + 23255550ULL * HZ / 1000000000ULL))
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#define NDELAY_SHIFT 41
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#if HZ > MAX_NDELAY_HZ
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#error "HZ > MAX_NDELAY_HZ"
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#endif
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void __delay(unsigned long cycles)
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{
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u64 t0 = get_cycles();
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while ((unsigned long)(get_cycles() - t0) < cycles)
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cpu_relax();
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}
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EXPORT_SYMBOL(__delay);
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void udelay(unsigned long usecs)
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{
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u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;
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if (unlikely(usecs > MAX_UDELAY_US)) {
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__delay((u64)usecs * riscv_timebase / 1000000ULL);
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return;
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}
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__delay(ucycles >> UDELAY_SHIFT);
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}
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EXPORT_SYMBOL(udelay);
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void ndelay(unsigned long nsecs)
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{
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/*
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* This doesn't bother checking for overflow, as it won't happen (it's
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* an hour) of delay.
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*/
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unsigned long long ncycles = nsecs * lpj_fine * NDELAY_MULT;
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__delay(ncycles >> NDELAY_SHIFT);
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}
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EXPORT_SYMBOL(ndelay);
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