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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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63d12e2323
This patch adds mode pin support to the sh7785lcr board. The harware allows the user to control the mode pins using dip switches S1 and S2, but from the software the pins are fixed to the factory default since we have no way to reading out this configuration from software. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
355 lines
7.8 KiB
C
355 lines
7.8 KiB
C
/*
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* Renesas Technology Corp. R0P7785LC0011RL Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/sm501.h>
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#include <linux/sm501-regs.h>
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#include <linux/fb.h>
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#include <linux/mtd/physmap.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/i2c-pca-platform.h>
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#include <linux/i2c-algo-pca.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <mach/sh7785lcr.h>
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#include <asm/heartbeat.h>
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#include <asm/clock.h>
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#include <cpu/sh7785.h>
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/*
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* NOTE: This board has 2 physical memory maps.
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* Please look at include/asm-sh/sh7785lcr.h or hardware manual.
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*/
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static struct resource heartbeat_resources[] = {
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[0] = {
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.start = PLD_LEDCR,
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.end = PLD_LEDCR,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct heartbeat_data heartbeat_data = {
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.regsize = 8,
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.dev = {
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.platform_data = &heartbeat_data,
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},
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.num_resources = ARRAY_SIZE(heartbeat_resources),
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.resource = heartbeat_resources,
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};
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static struct mtd_partition nor_flash_partitions[] = {
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{
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.name = "loader",
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.offset = 0x00000000,
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.size = 512 * 1024,
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},
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{
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.name = "bootenv",
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.offset = MTDPART_OFS_APPEND,
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.size = 512 * 1024,
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},
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{
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = 4 * 1024 * 1024,
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},
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{
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.name = "data",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data nor_flash_data = {
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.width = 4,
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.parts = nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(nor_flash_partitions),
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};
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static struct resource nor_flash_resources[] = {
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[0] = {
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.start = NOR_FLASH_ADDR,
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.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device nor_flash_device = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &nor_flash_data,
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},
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.num_resources = ARRAY_SIZE(nor_flash_resources),
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.resource = nor_flash_resources,
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};
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static struct resource r8a66597_usb_host_resources[] = {
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[0] = {
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.name = "r8a66597_hcd",
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.start = R8A66597_ADDR,
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.end = R8A66597_ADDR + R8A66597_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "r8a66597_hcd",
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.start = 2,
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.end = 2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device r8a66597_usb_host_device = {
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.name = "r8a66597_hcd",
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.id = -1,
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.dev = {
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.dma_mask = NULL,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
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.resource = r8a66597_usb_host_resources,
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};
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static struct resource sm501_resources[] = {
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[0] = {
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.start = SM107_MEM_ADDR,
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.end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = SM107_REG_ADDR,
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.end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = 10,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct fb_videomode sm501_default_mode_crt = {
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.pixclock = 35714, /* 28MHz */
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.xres = 640,
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.yres = 480,
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.left_margin = 105,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 39,
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.vsync_len = 2,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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};
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static struct fb_videomode sm501_default_mode_pnl = {
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.pixclock = 40000, /* 25MHz */
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.xres = 640,
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.yres = 480,
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.left_margin = 2,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 39,
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.vsync_len = 2,
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.sync = 0,
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};
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static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
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.def_bpp = 16,
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.def_mode = &sm501_default_mode_pnl,
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.flags = SM501FB_FLAG_USE_INIT_MODE |
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SM501FB_FLAG_USE_HWCURSOR |
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SM501FB_FLAG_USE_HWACCEL |
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SM501FB_FLAG_DISABLE_AT_EXIT |
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SM501FB_FLAG_PANEL_NO_VBIASEN,
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};
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static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
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.def_bpp = 16,
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.def_mode = &sm501_default_mode_crt,
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.flags = SM501FB_FLAG_USE_INIT_MODE |
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SM501FB_FLAG_USE_HWCURSOR |
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SM501FB_FLAG_USE_HWACCEL |
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SM501FB_FLAG_DISABLE_AT_EXIT,
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};
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static struct sm501_platdata_fb sm501_fb_pdata = {
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.fb_route = SM501_FB_OWN,
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.fb_crt = &sm501_pdata_fbsub_crt,
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.fb_pnl = &sm501_pdata_fbsub_pnl,
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};
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static struct sm501_initdata sm501_initdata = {
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.gpio_high = {
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.set = 0x00001fe0,
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.mask = 0x0,
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},
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.devices = 0,
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.mclk = 84 * 1000000,
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.m1xclk = 112 * 1000000,
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};
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static struct sm501_platdata sm501_platform_data = {
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.init = &sm501_initdata,
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.fb = &sm501_fb_pdata,
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};
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static struct platform_device sm501_device = {
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.name = "sm501",
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.id = -1,
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.dev = {
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.platform_data = &sm501_platform_data,
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},
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.num_resources = ARRAY_SIZE(sm501_resources),
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.resource = sm501_resources,
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};
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static struct resource i2c_resources[] = {
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[0] = {
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.start = PCA9564_ADDR,
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.end = PCA9564_ADDR + PCA9564_SIZE - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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},
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[1] = {
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.start = 12,
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.end = 12,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
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.gpio = 0,
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.i2c_clock_speed = I2C_PCA_CON_330kHz,
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.timeout = HZ,
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};
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static struct platform_device i2c_device = {
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.name = "i2c-pca-platform",
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.id = -1,
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.dev = {
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.platform_data = &i2c_platform_data,
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},
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.num_resources = ARRAY_SIZE(i2c_resources),
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.resource = i2c_resources,
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};
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static struct platform_device *sh7785lcr_devices[] __initdata = {
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&heartbeat_device,
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&nor_flash_device,
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&r8a66597_usb_host_device,
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&sm501_device,
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&i2c_device,
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};
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static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
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{
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I2C_BOARD_INFO("r2025sd", 0x32),
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},
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};
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static int __init sh7785lcr_devices_setup(void)
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{
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i2c_register_board_info(0, sh7785lcr_i2c_devices,
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ARRAY_SIZE(sh7785lcr_i2c_devices));
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return platform_add_devices(sh7785lcr_devices,
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ARRAY_SIZE(sh7785lcr_devices));
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}
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__initcall(sh7785lcr_devices_setup);
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/* Initialize IRQ setting */
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void __init init_sh7785lcr_IRQ(void)
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{
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plat_irq_setup_pins(IRQ_MODE_IRQ7654);
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plat_irq_setup_pins(IRQ_MODE_IRQ3210);
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}
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static int sh7785lcr_clk_init(void)
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{
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struct clk *clk;
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int ret;
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clk = clk_get(NULL, "extal");
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if (!clk || IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_set_rate(clk, 33333333);
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clk_put(clk);
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return ret;
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}
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static void sh7785lcr_power_off(void)
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{
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unsigned char *p;
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p = ioremap(PLD_POFCR, PLD_POFCR + 1);
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if (!p) {
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printk(KERN_ERR "%s: ioremap error.\n", __func__);
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return;
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}
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*p = 0x01;
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iounmap(p);
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set_bl_bit();
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while (1)
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cpu_relax();
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}
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/* Initialize the board */
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static void __init sh7785lcr_setup(char **cmdline_p)
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{
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void __iomem *sm501_reg;
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printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
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pm_power_off = sh7785lcr_power_off;
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/* sm501 DRAM configuration */
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sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
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writel(0x000307c2, sm501_reg);
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}
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/* Return the board specific boot mode pin configuration */
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static int sh7785lcr_mode_pins(void)
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{
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int value = 0;
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/* These are the factory default settings of S1 and S2.
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* If you change these dip switches then you will need to
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* adjust the values below as well.
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*/
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value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */
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value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */
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value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */
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value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */
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value |= 1 << MODE_PIN_MODE8; /* Little Endian */
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value |= 1 << MODE_PIN_MODE9; /* Master Mode */
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value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */
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return value;
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}
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/*
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* The Machine Vector
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*/
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static struct sh_machine_vector mv_sh7785lcr __initmv = {
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.mv_name = "SH7785LCR",
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.mv_setup = sh7785lcr_setup,
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.mv_clk_init = sh7785lcr_clk_init,
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.mv_init_irq = init_sh7785lcr_IRQ,
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.mv_mode_pins = sh7785lcr_mode_pins,
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};
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