mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 19:26:40 +07:00
8af4baa708
This patch fixes faulty behaviour in a setup where the input clock for the SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must not be configured as output pin. Otherwise the input clock is messed up horribly. This patch makes it possible to use the CLKR/CLKX pin rather than CLKS to inject a reference clock in setups where McBSP is master and not both rx and tx are used. However for this to work it has to be ensured that set_dai_sysclk() is called after set_dai_fmt(). This was tested on a beagleboard-xm using McBSP1 to drive a i2s DAC through the tx lines (CLKX,FSX,DX). Using this patch the CLKR pin is used to inject an external reference clock. Signed-off-by: Thomas Niederprüm <niederp@physik.uni-kl.de> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
858 lines
22 KiB
C
858 lines
22 KiB
C
/*
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* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
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* Peter Ujfalusi <peter.ujfalusi@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/omap-pcm.h>
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#include <linux/platform_data/asoc-ti-mcbsp.h>
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#include "mcbsp.h"
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#include "omap-mcbsp.h"
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#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
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#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
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xhandler_get, xhandler_put) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = omap_mcbsp_st_info_volsw, \
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.get = xhandler_get, .put = xhandler_put, \
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.private_value = (unsigned long) &(struct soc_mixer_control) \
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{.min = xmin, .max = xmax} }
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enum {
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OMAP_MCBSP_WORD_8 = 0,
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OMAP_MCBSP_WORD_12,
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OMAP_MCBSP_WORD_16,
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OMAP_MCBSP_WORD_20,
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OMAP_MCBSP_WORD_24,
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OMAP_MCBSP_WORD_32,
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};
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/*
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* Stream DMA parameters. DMA request line and port address are set runtime
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* since they are different between OMAP1 and later OMAPs
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*/
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static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
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unsigned int packet_size)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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int words;
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/*
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* Configure McBSP threshold based on either:
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* packet_size, when the sDMA is in packet mode, or based on the
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* period size in THRESHOLD mode, otherwise use McBSP threshold = 1
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* for mono streams.
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*/
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if (packet_size)
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words = packet_size;
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else
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words = 1;
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/* Configure McBSP internal buffer usage */
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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omap_mcbsp_set_tx_threshold(mcbsp, words);
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else
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omap_mcbsp_set_rx_threshold(mcbsp, words);
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}
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static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct snd_interval *buffer_size = hw_param_interval(params,
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SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
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struct snd_interval *channels = hw_param_interval(params,
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SNDRV_PCM_HW_PARAM_CHANNELS);
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struct omap_mcbsp *mcbsp = rule->private;
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struct snd_interval frames;
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int size;
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snd_interval_any(&frames);
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size = mcbsp->pdata->buffer_size;
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frames.min = size / channels->min;
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frames.integer = 1;
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return snd_interval_refine(buffer_size, &frames);
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}
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static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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int err = 0;
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if (!cpu_dai->active)
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err = omap_mcbsp_request(mcbsp);
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/*
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* OMAP3 McBSP FIFO is word structured.
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* McBSP2 has 1024 + 256 = 1280 word long buffer,
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* McBSP1,3,4,5 has 128 word long buffer
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* This means that the size of the FIFO depends on the sample format.
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* For example on McBSP3:
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* 16bit samples: size is 128 * 2 = 256 bytes
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* 32bit samples: size is 128 * 4 = 512 bytes
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* It is simpler to place constraint for buffer and period based on
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* channels.
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* McBSP3 as example again (16 or 32 bit samples):
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* 1 channel (mono): size is 128 frames (128 words)
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* 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
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* 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
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*/
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if (mcbsp->pdata->buffer_size) {
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/*
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* Rule for the buffer size. We should not allow
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* smaller buffer than the FIFO size to avoid underruns.
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* This applies only for the playback stream.
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
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omap_mcbsp_hwrule_min_buffersize,
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mcbsp,
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SNDRV_PCM_HW_PARAM_CHANNELS, -1);
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/* Make sure, that the period size is always even */
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
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}
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return err;
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}
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static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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if (!cpu_dai->active) {
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omap_mcbsp_free(mcbsp);
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mcbsp->configured = 0;
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}
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}
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static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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mcbsp->active++;
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omap_mcbsp_start(mcbsp, play, !play);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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omap_mcbsp_stop(mcbsp, play, !play);
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mcbsp->active--;
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break;
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default:
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err = -EINVAL;
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}
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return err;
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}
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static snd_pcm_sframes_t omap_mcbsp_dai_delay(
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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u16 fifo_use;
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snd_pcm_sframes_t delay;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
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else
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fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
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/*
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* Divide the used locations with the channel count to get the
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* FIFO usage in samples (don't care about partial samples in the
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* buffer).
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*/
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delay = fifo_use / substream->runtime->channels;
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return delay;
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}
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static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
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struct snd_dmaengine_dai_dma_data *dma_data;
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int wlen, channels, wpf;
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int pkt_size = 0;
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unsigned int format, div, framesize, master;
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dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
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channels = params_channels(params);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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wlen = 16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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wlen = 32;
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break;
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default:
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return -EINVAL;
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}
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if (mcbsp->pdata->buffer_size) {
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if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
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int period_words, max_thrsh;
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int divider = 0;
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period_words = params_period_bytes(params) / (wlen / 8);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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max_thrsh = mcbsp->max_tx_thres;
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else
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max_thrsh = mcbsp->max_rx_thres;
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/*
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* Use sDMA packet mode if McBSP is in threshold mode:
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* If period words less than the FIFO size the packet
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* size is set to the number of period words, otherwise
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* Look for the biggest threshold value which divides
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* the period size evenly.
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*/
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divider = period_words / max_thrsh;
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if (period_words % max_thrsh)
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divider++;
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while (period_words % divider &&
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divider < period_words)
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divider++;
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if (divider == period_words)
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return -EINVAL;
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pkt_size = period_words / divider;
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} else if (channels > 1) {
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/* Use packet mode for non mono streams */
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pkt_size = channels;
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}
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omap_mcbsp_set_threshold(substream, pkt_size);
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}
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dma_data->maxburst = pkt_size;
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if (mcbsp->configured) {
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/* McBSP already configured by another stream */
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return 0;
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}
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regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
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regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
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regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
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regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
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format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
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wpf = channels;
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if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
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format == SND_SOC_DAIFMT_LEFT_J)) {
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/* Use dual-phase frames */
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regs->rcr2 |= RPHASE;
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regs->xcr2 |= XPHASE;
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/* Set 1 word per (McBSP) frame for phase1 and phase2 */
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wpf--;
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regs->rcr2 |= RFRLEN2(wpf - 1);
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regs->xcr2 |= XFRLEN2(wpf - 1);
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}
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regs->rcr1 |= RFRLEN1(wpf - 1);
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regs->xcr1 |= XFRLEN1(wpf - 1);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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/* Set word lengths */
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regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
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regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
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regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
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regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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/* Set word lengths */
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regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
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regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
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regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
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regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
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break;
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default:
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/* Unsupported PCM format */
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return -EINVAL;
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}
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/* In McBSP master modes, FRAME (i.e. sample rate) is generated
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* by _counting_ BCLKs. Calculate frame size in BCLKs */
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master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
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if (master == SND_SOC_DAIFMT_CBS_CFS) {
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div = mcbsp->clk_div ? mcbsp->clk_div : 1;
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framesize = (mcbsp->in_freq / div) / params_rate(params);
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if (framesize < wlen * channels) {
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printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
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"channels\n", __func__);
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return -EINVAL;
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}
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} else
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framesize = wlen * channels;
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/* Set FS period and length in terms of bit clock periods */
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regs->srgr2 &= ~FPER(0xfff);
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regs->srgr1 &= ~FWID(0xff);
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switch (format) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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regs->srgr2 |= FPER(framesize - 1);
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regs->srgr1 |= FWID((framesize >> 1) - 1);
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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regs->srgr2 |= FPER(framesize - 1);
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regs->srgr1 |= FWID(0);
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break;
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}
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omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
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mcbsp->wlen = wlen;
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mcbsp->configured = 1;
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return 0;
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}
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/*
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* This must be called before _set_clkdiv and _set_sysclk since McBSP register
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* cache is initialized here
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*/
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static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
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bool inv_fs = false;
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if (mcbsp->configured)
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return 0;
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mcbsp->fmt = fmt;
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memset(regs, 0, sizeof(*regs));
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/* Generic McBSP register settings */
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regs->spcr2 |= XINTM(3) | FREE;
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regs->spcr1 |= RINTM(3);
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/* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
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if (!mcbsp->pdata->has_ccr) {
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regs->rcr2 |= RFIG;
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regs->xcr2 |= XFIG;
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}
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/* Configure XCCR/RCCR only for revisions which have ccr registers */
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if (mcbsp->pdata->has_ccr) {
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regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
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regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* 1-bit data delay */
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regs->rcr2 |= RDATDLY(1);
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regs->xcr2 |= XDATDLY(1);
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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/* 0-bit data delay */
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regs->rcr2 |= RDATDLY(0);
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regs->xcr2 |= XDATDLY(0);
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regs->spcr1 |= RJUST(2);
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/* Invert FS polarity configuration */
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inv_fs = true;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/* 1-bit data delay */
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regs->rcr2 |= RDATDLY(1);
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regs->xcr2 |= XDATDLY(1);
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/* Invert FS polarity configuration */
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inv_fs = true;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* 0-bit data delay */
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regs->rcr2 |= RDATDLY(0);
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regs->xcr2 |= XDATDLY(0);
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/* Invert FS polarity configuration */
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inv_fs = true;
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break;
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default:
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/* Unsupported data format */
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* McBSP master. Set FS and bit clocks as outputs */
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regs->pcr0 |= FSXM | FSRM |
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CLKXM | CLKRM;
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/* Sample rate generator drives the FS */
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regs->srgr2 |= FSGM;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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/* McBSP slave. FS clock as output */
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regs->srgr2 |= FSGM;
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regs->pcr0 |= FSXM | FSRM;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* McBSP slave */
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break;
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default:
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/* Unsupported master/slave configuration */
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|
return -EINVAL;
|
|
}
|
|
|
|
/* Set bit clock (CLKX/CLKR) and FS polarities */
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
/*
|
|
* Normal BCLK + FS.
|
|
* FS active low. TX data driven on falling edge of bit clock
|
|
* and RX data sampled on rising edge of bit clock.
|
|
*/
|
|
regs->pcr0 |= FSXP | FSRP |
|
|
CLKXP | CLKRP;
|
|
break;
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
regs->pcr0 |= CLKXP | CLKRP;
|
|
break;
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
regs->pcr0 |= FSXP | FSRP;
|
|
break;
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
if (inv_fs == true)
|
|
regs->pcr0 ^= FSXP | FSRP;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
|
|
int div_id, int div)
|
|
{
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
|
|
|
|
if (div_id != OMAP_MCBSP_CLKGDV)
|
|
return -ENODEV;
|
|
|
|
mcbsp->clk_div = div;
|
|
regs->srgr1 &= ~CLKGDV(0xff);
|
|
regs->srgr1 |= CLKGDV(div - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
|
|
int clk_id, unsigned int freq,
|
|
int dir)
|
|
{
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
|
|
int err = 0;
|
|
|
|
if (mcbsp->active) {
|
|
if (freq == mcbsp->in_freq)
|
|
return 0;
|
|
else
|
|
return -EBUSY;
|
|
}
|
|
|
|
mcbsp->in_freq = freq;
|
|
regs->srgr2 &= ~CLKSM;
|
|
regs->pcr0 &= ~SCLKME;
|
|
|
|
switch (clk_id) {
|
|
case OMAP_MCBSP_SYSCLK_CLK:
|
|
regs->srgr2 |= CLKSM;
|
|
break;
|
|
case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
|
|
if (mcbsp_omap1()) {
|
|
err = -EINVAL;
|
|
break;
|
|
}
|
|
err = omap2_mcbsp_set_clks_src(mcbsp,
|
|
MCBSP_CLKS_PRCM_SRC);
|
|
break;
|
|
case OMAP_MCBSP_SYSCLK_CLKS_EXT:
|
|
if (mcbsp_omap1()) {
|
|
err = 0;
|
|
break;
|
|
}
|
|
err = omap2_mcbsp_set_clks_src(mcbsp,
|
|
MCBSP_CLKS_PAD_SRC);
|
|
break;
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLKX_EXT:
|
|
regs->srgr2 |= CLKSM;
|
|
regs->pcr0 |= SCLKME;
|
|
/*
|
|
* If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
|
|
* disable output on those pins. This enables to inject the
|
|
* reference clock through CLKX/CLKR. For this to work
|
|
* set_dai_sysclk() _needs_ to be called after set_dai_fmt().
|
|
*/
|
|
regs->pcr0 &= ~CLKXM;
|
|
break;
|
|
case OMAP_MCBSP_SYSCLK_CLKR_EXT:
|
|
regs->pcr0 |= SCLKME;
|
|
/* Disable ouput on CLKR pin in master mode */
|
|
regs->pcr0 &= ~CLKRM;
|
|
break;
|
|
default:
|
|
err = -ENODEV;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops mcbsp_dai_ops = {
|
|
.startup = omap_mcbsp_dai_startup,
|
|
.shutdown = omap_mcbsp_dai_shutdown,
|
|
.trigger = omap_mcbsp_dai_trigger,
|
|
.delay = omap_mcbsp_dai_delay,
|
|
.hw_params = omap_mcbsp_dai_hw_params,
|
|
.set_fmt = omap_mcbsp_dai_set_dai_fmt,
|
|
.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
|
|
.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
|
|
};
|
|
|
|
static int omap_mcbsp_probe(struct snd_soc_dai *dai)
|
|
{
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
|
|
|
|
pm_runtime_enable(mcbsp->dev);
|
|
|
|
snd_soc_dai_init_dma_data(dai,
|
|
&mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
|
|
&mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_mcbsp_remove(struct snd_soc_dai *dai)
|
|
{
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
|
|
|
|
pm_runtime_disable(mcbsp->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_dai_driver omap_mcbsp_dai = {
|
|
.probe = omap_mcbsp_probe,
|
|
.remove = omap_mcbsp_remove,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 16,
|
|
.rates = OMAP_MCBSP_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 16,
|
|
.rates = OMAP_MCBSP_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &mcbsp_dai_ops,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver omap_mcbsp_component = {
|
|
.name = "omap-mcbsp",
|
|
};
|
|
|
|
static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_info *uinfo)
|
|
{
|
|
struct soc_mixer_control *mc =
|
|
(struct soc_mixer_control *)kcontrol->private_value;
|
|
int max = mc->max;
|
|
int min = mc->min;
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
|
uinfo->count = 1;
|
|
uinfo->value.integer.min = min;
|
|
uinfo->value.integer.max = max;
|
|
return 0;
|
|
}
|
|
|
|
#define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \
|
|
static int \
|
|
omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
|
|
struct snd_ctl_elem_value *uc) \
|
|
{ \
|
|
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
|
|
struct soc_mixer_control *mc = \
|
|
(struct soc_mixer_control *)kc->private_value; \
|
|
int max = mc->max; \
|
|
int min = mc->min; \
|
|
int val = uc->value.integer.value[0]; \
|
|
\
|
|
if (val < min || val > max) \
|
|
return -EINVAL; \
|
|
\
|
|
/* OMAP McBSP implementation uses index values 0..4 */ \
|
|
return omap_st_set_chgain(mcbsp, channel, val); \
|
|
} \
|
|
\
|
|
static int \
|
|
omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
|
|
struct snd_ctl_elem_value *uc) \
|
|
{ \
|
|
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
|
|
s16 chgain; \
|
|
\
|
|
if (omap_st_get_chgain(mcbsp, channel, &chgain)) \
|
|
return -EAGAIN; \
|
|
\
|
|
uc->value.integer.value[0] = chgain; \
|
|
return 0; \
|
|
}
|
|
|
|
OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
|
|
OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
|
|
|
|
static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
|
|
u8 value = ucontrol->value.integer.value[0];
|
|
|
|
if (value == omap_st_is_enabled(mcbsp))
|
|
return 0;
|
|
|
|
if (value)
|
|
omap_st_enable(mcbsp);
|
|
else
|
|
omap_st_disable(mcbsp);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
|
ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
|
|
return 0;
|
|
}
|
|
|
|
#define OMAP_MCBSP_ST_CONTROLS(port) \
|
|
static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
|
|
SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \
|
|
omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \
|
|
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
|
|
-32768, 32767, \
|
|
omap_mcbsp_get_st_ch0_volume, \
|
|
omap_mcbsp_set_st_ch0_volume), \
|
|
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
|
|
-32768, 32767, \
|
|
omap_mcbsp_get_st_ch1_volume, \
|
|
omap_mcbsp_set_st_ch1_volume), \
|
|
}
|
|
|
|
OMAP_MCBSP_ST_CONTROLS(2);
|
|
OMAP_MCBSP_ST_CONTROLS(3);
|
|
|
|
int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd, int port_id)
|
|
{
|
|
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
|
struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
|
if (!mcbsp->st_data) {
|
|
dev_warn(mcbsp->dev, "No sidetone data for port\n");
|
|
return 0;
|
|
}
|
|
|
|
switch (port_id) {
|
|
case 2: /* McBSP 2 */
|
|
return snd_soc_add_dai_controls(cpu_dai,
|
|
omap_mcbsp2_st_controls,
|
|
ARRAY_SIZE(omap_mcbsp2_st_controls));
|
|
case 3: /* McBSP 3 */
|
|
return snd_soc_add_dai_controls(cpu_dai,
|
|
omap_mcbsp3_st_controls,
|
|
ARRAY_SIZE(omap_mcbsp3_st_controls));
|
|
default:
|
|
dev_err(mcbsp->dev, "Port %d not supported\n", port_id);
|
|
break;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
|
|
|
|
static struct omap_mcbsp_platform_data omap2420_pdata = {
|
|
.reg_step = 4,
|
|
.reg_size = 2,
|
|
};
|
|
|
|
static struct omap_mcbsp_platform_data omap2430_pdata = {
|
|
.reg_step = 4,
|
|
.reg_size = 4,
|
|
.has_ccr = true,
|
|
};
|
|
|
|
static struct omap_mcbsp_platform_data omap3_pdata = {
|
|
.reg_step = 4,
|
|
.reg_size = 4,
|
|
.has_ccr = true,
|
|
.has_wakeup = true,
|
|
};
|
|
|
|
static struct omap_mcbsp_platform_data omap4_pdata = {
|
|
.reg_step = 4,
|
|
.reg_size = 4,
|
|
.has_ccr = true,
|
|
.has_wakeup = true,
|
|
};
|
|
|
|
static const struct of_device_id omap_mcbsp_of_match[] = {
|
|
{
|
|
.compatible = "ti,omap2420-mcbsp",
|
|
.data = &omap2420_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,omap2430-mcbsp",
|
|
.data = &omap2430_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,omap3-mcbsp",
|
|
.data = &omap3_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,omap4-mcbsp",
|
|
.data = &omap4_pdata,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
|
|
|
|
static int asoc_mcbsp_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct omap_mcbsp *mcbsp;
|
|
const struct of_device_id *match;
|
|
int ret;
|
|
|
|
match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
|
|
if (match) {
|
|
struct device_node *node = pdev->dev.of_node;
|
|
int buffer_size;
|
|
|
|
pdata = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct omap_mcbsp_platform_data),
|
|
GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
memcpy(pdata, match->data, sizeof(*pdata));
|
|
if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
|
|
pdata->buffer_size = buffer_size;
|
|
} else if (!pdata) {
|
|
dev_err(&pdev->dev, "missing platform data.\n");
|
|
return -EINVAL;
|
|
}
|
|
mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
|
|
if (!mcbsp)
|
|
return -ENOMEM;
|
|
|
|
mcbsp->id = pdev->id;
|
|
mcbsp->pdata = pdata;
|
|
mcbsp->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, mcbsp);
|
|
|
|
ret = omap_mcbsp_init(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev,
|
|
&omap_mcbsp_component,
|
|
&omap_mcbsp_dai, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return omap_pcm_platform_register(&pdev->dev);
|
|
}
|
|
|
|
static int asoc_mcbsp_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
|
|
|
|
if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
|
|
mcbsp->pdata->ops->free(mcbsp->id);
|
|
|
|
omap_mcbsp_sysfs_remove(mcbsp);
|
|
|
|
clk_put(mcbsp->fclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver asoc_mcbsp_driver = {
|
|
.driver = {
|
|
.name = "omap-mcbsp",
|
|
.of_match_table = omap_mcbsp_of_match,
|
|
},
|
|
|
|
.probe = asoc_mcbsp_probe,
|
|
.remove = asoc_mcbsp_remove,
|
|
};
|
|
|
|
module_platform_driver(asoc_mcbsp_driver);
|
|
|
|
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
|
|
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:omap-mcbsp");
|