Palmer Dabbelt 62b0194368 clocksource: new RISC-V SBI timer driver ... The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-08-13 08:31:31 -07:00
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configs	RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig	2018-06-11 09:16:24 -07:00
include	clocksource: new RISC-V SBI timer driver	2018-08-13 08:31:31 -07:00
kernel	clocksource: new RISC-V SBI timer driver	2018-08-13 08:31:31 -07:00
lib	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
mm	RISC-V: Add conditional macro for zone of DMA32	2018-07-04 13:53:21 -07:00
Kconfig	RISC-V: Select GENERIC_UCMPDI2 on RV32I	2018-07-04 13:53:33 -07:00
Makefile	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00