Kuppuswamy Sathyanarayanan 62a7b9c859 platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read ... To maintain the uniformity in accessing GCR registers, this patch modifies the S0ix counter read function to use GCR address base instead of ipc address base. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Tested-by: Shanth Murthy <shanth.murthy@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>		2017-04-28 21:51:28 +03:00
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chrome	- Core Frameworks	2017-02-23 08:18:01 -08:00
goldfish	goldfish: Sanitize the broken interrupt handler	2017-02-15 08:49:58 -08:00
mips	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	2016-05-19 10:02:26 -07:00
olpc	platform/olpc: Make ec explicitly non-modular	2016-08-28 22:31:52 -07:00
x86	platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read	2017-04-28 21:51:28 +03:00
Kconfig	goldfish: refactor goldfish platform configs	2016-01-28 23:34:36 -08:00
Makefile	MIPS: Loongson-3: Add CPU Hwmon platform driver	2015-04-01 17:22:17 +02:00