mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 01:37:41 +07:00
86e06f026b
The name "pmicintc" is ambiguous: there is a second power management IC named PM8901 on these systems, and it is also an interrupt controller. To make things clear, just name the node alias "pm8058", this in unambigous and has all information we need. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
434 lines
10 KiB
Plaintext
434 lines
10 KiB
Plaintext
/dts-v1/;
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm MSM8660";
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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cpu-pmu {
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compatible = "qcom,scorpion-mp-pmu";
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interrupts = <1 9 0x304>;
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};
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clocks {
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cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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tlmm: pinctrl@800000 {
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compatible = "qcom,msm8660-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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gsbi12: gsbi@19c00000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x19c00000 0x100>;
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clocks = <&gcc GSBI12_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi12_serial: serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 IRQ_TYPE_NONE>;
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clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi12_i2c: i2c@19c80000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x19c80000 0x1000>;
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interrupts = <0 196 IRQ_TYPE_NONE>;
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clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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external-bus@1a100000 {
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compatible = "qcom,msm8660-ebi2";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x1a800000 0x00800000>,
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<1 0x0 0x1b000000 0x00800000>,
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<2 0x0 0x1b800000 0x00800000>,
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<3 0x0 0x1d000000 0x08000000>,
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<4 0x0 0x1c800000 0x00800000>,
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<5 0x0 0x1c000000 0x00800000>;
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reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
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reg-names = "ebi2", "xmem";
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clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
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clock-names = "ebi2x", "ebi2";
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status = "disabled";
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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pm8058: pmic@0 {
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compatible = "qcom,pm8058";
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interrupt-parent = <&tlmm>;
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interrupts = <88 8>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8058_gpio: gpio@150 {
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compatible = "qcom,pm8058-gpio",
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"qcom,ssbi-gpio";
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reg = <0x150>;
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interrupt-parent = <&pm8058>;
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interrupts = <192 IRQ_TYPE_NONE>,
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<193 IRQ_TYPE_NONE>,
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<194 IRQ_TYPE_NONE>,
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<195 IRQ_TYPE_NONE>,
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<196 IRQ_TYPE_NONE>,
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<197 IRQ_TYPE_NONE>,
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<198 IRQ_TYPE_NONE>,
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<199 IRQ_TYPE_NONE>,
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<200 IRQ_TYPE_NONE>,
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<201 IRQ_TYPE_NONE>,
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<202 IRQ_TYPE_NONE>,
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<203 IRQ_TYPE_NONE>,
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<204 IRQ_TYPE_NONE>,
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<205 IRQ_TYPE_NONE>,
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<206 IRQ_TYPE_NONE>,
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<207 IRQ_TYPE_NONE>,
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<208 IRQ_TYPE_NONE>,
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<209 IRQ_TYPE_NONE>,
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<210 IRQ_TYPE_NONE>,
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<211 IRQ_TYPE_NONE>,
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<212 IRQ_TYPE_NONE>,
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<213 IRQ_TYPE_NONE>,
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<214 IRQ_TYPE_NONE>,
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<215 IRQ_TYPE_NONE>,
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<216 IRQ_TYPE_NONE>,
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<217 IRQ_TYPE_NONE>,
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<218 IRQ_TYPE_NONE>,
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<219 IRQ_TYPE_NONE>,
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<220 IRQ_TYPE_NONE>,
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<221 IRQ_TYPE_NONE>,
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<222 IRQ_TYPE_NONE>,
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<223 IRQ_TYPE_NONE>,
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<224 IRQ_TYPE_NONE>,
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<225 IRQ_TYPE_NONE>,
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<226 IRQ_TYPE_NONE>,
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<227 IRQ_TYPE_NONE>,
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<228 IRQ_TYPE_NONE>,
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<229 IRQ_TYPE_NONE>,
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<230 IRQ_TYPE_NONE>,
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<231 IRQ_TYPE_NONE>,
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<232 IRQ_TYPE_NONE>,
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<233 IRQ_TYPE_NONE>,
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<234 IRQ_TYPE_NONE>,
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<235 IRQ_TYPE_NONE>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pm8058_mpps: mpps@50 {
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compatible = "qcom,pm8058-mpp",
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"qcom,ssbi-mpp";
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reg = <0x50>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&pm8058>;
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interrupts =
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<128 IRQ_TYPE_NONE>,
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<129 IRQ_TYPE_NONE>,
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<130 IRQ_TYPE_NONE>,
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<131 IRQ_TYPE_NONE>,
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<132 IRQ_TYPE_NONE>,
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<133 IRQ_TYPE_NONE>,
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<134 IRQ_TYPE_NONE>,
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<135 IRQ_TYPE_NONE>,
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<136 IRQ_TYPE_NONE>,
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<137 IRQ_TYPE_NONE>,
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<138 IRQ_TYPE_NONE>,
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<139 IRQ_TYPE_NONE>;
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};
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pwrkey@1c {
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compatible = "qcom,pm8058-pwrkey";
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reg = <0x1c>;
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interrupt-parent = <&pm8058>;
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interrupts = <50 1>, <51 1>;
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debounce = <15625>;
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pull-up;
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};
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keypad@148 {
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compatible = "qcom,pm8058-keypad";
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reg = <0x148>;
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interrupt-parent = <&pm8058>;
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interrupts = <74 1>, <75 1>;
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debounce = <15>;
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scan-delay = <32>;
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row-hold = <91500>;
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};
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rtc@1e8 {
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compatible = "qcom,pm8058-rtc";
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reg = <0x1e8>;
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interrupt-parent = <&pm8058>;
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interrupts = <39 1>;
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allow-set-time;
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};
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vibrator@4a {
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compatible = "qcom,pm8058-vib";
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reg = <0x4a>;
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};
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};
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};
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l2cc: clock-controller@2082000 {
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compatible = "syscon";
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reg = <0x02082000 0x1000>;
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};
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rpm: rpm@104000 {
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compatible = "qcom,rpm-msm8660";
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reg = <0x00104000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack", "err", "wakeup";
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clocks = <&gcc RPM_MSG_RAM_H_CLK>;
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clock-names = "ram";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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pm8901-regulators {
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compatible = "qcom,rpm-pm8901-regulators";
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pm8901_l0: l0 {};
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pm8901_l1: l1 {};
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pm8901_l2: l2 {};
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pm8901_l3: l3 {};
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pm8901_l4: l4 {};
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pm8901_l5: l5 {};
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pm8901_l6: l6 {};
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/* S0 and S1 Handled as SAW regulators by SPM */
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pm8901_s2: s2 {};
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pm8901_s3: s3 {};
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pm8901_s4: s4 {};
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pm8901_lvs0: lvs0 {};
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pm8901_lvs1: lvs1 {};
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pm8901_lvs2: lvs2 {};
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pm8901_lvs3: lvs3 {};
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pm8901_mvs: mvs {};
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};
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pm8058-regulators {
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compatible = "qcom,rpm-pm8058-regulators";
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pm8058_l0: l0 {};
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pm8058_l1: l1 {};
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pm8058_l2: l2 {};
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pm8058_l3: l3 {};
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pm8058_l4: l4 {};
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pm8058_l5: l5 {};
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pm8058_l6: l6 {};
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pm8058_l7: l7 {};
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pm8058_l8: l8 {};
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pm8058_l9: l9 {};
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pm8058_l10: l10 {};
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pm8058_l11: l11 {};
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pm8058_l12: l12 {};
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pm8058_l13: l13 {};
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pm8058_l14: l14 {};
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pm8058_l15: l15 {};
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pm8058_l16: l16 {};
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pm8058_l17: l17 {};
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pm8058_l18: l18 {};
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pm8058_l19: l19 {};
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pm8058_l20: l20 {};
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pm8058_l21: l21 {};
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pm8058_l22: l22 {};
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pm8058_l23: l23 {};
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pm8058_l24: l24 {};
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pm8058_l25: l25 {};
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pm8058_s0: s0 {};
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pm8058_s1: s1 {};
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pm8058_s2: s2 {};
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pm8058_s3: s3 {};
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pm8058_s4: s4 {};
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pm8058_lvs0: lvs0 {};
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pm8058_lvs1: lvs1 {};
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pm8058_ncp: ncp {};
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x8000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <48000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc3: sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x8000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <48000000>;
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no-1-8-v;
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};
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sdcc5: sdcc@12200000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12200000 0x8000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <48000000>;
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-msm8660", "syscon";
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reg = <0x1a400000 0x100>;
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};
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};
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};
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