mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 20:56:41 +07:00
ed05e204af
Rename the argument "virq" to just "irq", this IRQ isn't any more "virtual" than any other Linux IRQ number, we use "hwirq" for the actual hw-numbers, "virq" is just bogus. When doing this I see that the hwirq argument is used for mapping rather than the Linux IRQ in the map function. This doesn't look right. Use the Linux IRQ instead. I cannot test this patch so I don't know if the mapping change is correct, however since absolutely every other driver does it the other way around this doesn't look sound at all. Please help out with review. Cc: Vipul Kumar Samar <vipulkumar.samar@st.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Gabriel Fernandez <gabriel.fernandez@st.com> Cc: Jean-Nicolas Graux <jean-nicolas.graux@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
462 lines
11 KiB
C
462 lines
11 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License, version 2
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/mfd/stmpe.h>
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/*
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* These registers are modified under the irq bus lock and cached to avoid
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* unnecessary writes in bus_sync_unlock.
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*/
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enum { REG_RE, REG_FE, REG_IE };
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#define CACHE_NR_REGS 3
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#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
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struct stmpe_gpio {
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struct gpio_chip chip;
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struct stmpe *stmpe;
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struct device *dev;
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struct mutex irq_lock;
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struct irq_domain *domain;
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int irq_base;
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unsigned norequest_mask;
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/* Caches of interrupt control registers for bus_lock */
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u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
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u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
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};
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static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
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{
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return container_of(chip, struct stmpe_gpio, chip);
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}
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static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
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u8 mask = 1 << (offset % 8);
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int ret;
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ret = stmpe_reg_read(stmpe, reg);
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if (ret < 0)
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return ret;
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return !!(ret & mask);
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}
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static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
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u8 reg = stmpe->regs[which] - (offset / 8);
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u8 mask = 1 << (offset % 8);
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/*
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* Some variants have single register for gpio set/clear functionality.
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* For them we need to write 0 to clear and 1 to set.
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*/
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if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
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stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
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else
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stmpe_reg_write(stmpe, reg, mask);
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}
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static int stmpe_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int val)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
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u8 mask = 1 << (offset % 8);
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stmpe_gpio_set(chip, offset, val);
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return stmpe_set_bits(stmpe, reg, mask, mask);
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}
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static int stmpe_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
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u8 mask = 1 << (offset % 8);
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return stmpe_set_bits(stmpe, reg, mask, 0);
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}
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static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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return irq_create_mapping(stmpe_gpio->domain, offset);
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}
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static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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if (stmpe_gpio->norequest_mask & (1 << offset))
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return -EINVAL;
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return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
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}
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static struct gpio_chip template_chip = {
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.label = "stmpe",
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.owner = THIS_MODULE,
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.direction_input = stmpe_gpio_direction_input,
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.get = stmpe_gpio_get,
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.direction_output = stmpe_gpio_direction_output,
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.set = stmpe_gpio_set,
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.to_irq = stmpe_gpio_to_irq,
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.request = stmpe_gpio_request,
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.can_sleep = 1,
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};
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static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = 1 << (offset % 8);
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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/* STMPE801 doesn't have RE and FE registers */
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if (stmpe_gpio->stmpe->partnum == STMPE801)
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return 0;
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if (type == IRQ_TYPE_EDGE_RISING)
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stmpe_gpio->regs[REG_RE][regoffset] |= mask;
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else
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stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
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if (type == IRQ_TYPE_EDGE_FALLING)
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stmpe_gpio->regs[REG_FE][regoffset] |= mask;
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else
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stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
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return 0;
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}
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static void stmpe_gpio_irq_lock(struct irq_data *d)
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{
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struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
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mutex_lock(&stmpe_gpio->irq_lock);
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}
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static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
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{
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struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
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static const u8 regmap[] = {
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[REG_RE] = STMPE_IDX_GPRER_LSB,
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[REG_FE] = STMPE_IDX_GPFER_LSB,
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[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
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};
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int i, j;
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for (i = 0; i < CACHE_NR_REGS; i++) {
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/* STMPE801 doesn't have RE and FE registers */
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if ((stmpe->partnum == STMPE801) &&
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(i != REG_IE))
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continue;
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for (j = 0; j < num_banks; j++) {
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u8 old = stmpe_gpio->oldregs[i][j];
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u8 new = stmpe_gpio->regs[i][j];
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if (new == old)
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continue;
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stmpe_gpio->oldregs[i][j] = new;
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stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
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}
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}
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mutex_unlock(&stmpe_gpio->irq_lock);
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}
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static void stmpe_gpio_irq_mask(struct irq_data *d)
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{
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struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = 1 << (offset % 8);
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stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
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}
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static void stmpe_gpio_irq_unmask(struct irq_data *d)
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{
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struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = 1 << (offset % 8);
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stmpe_gpio->regs[REG_IE][regoffset] |= mask;
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}
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static struct irq_chip stmpe_gpio_irq_chip = {
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.name = "stmpe-gpio",
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.irq_bus_lock = stmpe_gpio_irq_lock,
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.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
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.irq_mask = stmpe_gpio_irq_mask,
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.irq_unmask = stmpe_gpio_irq_unmask,
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.irq_set_type = stmpe_gpio_irq_set_type,
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};
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static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
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{
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struct stmpe_gpio *stmpe_gpio = dev;
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
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u8 status[num_banks];
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int ret;
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int i;
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ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
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if (ret < 0)
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return IRQ_NONE;
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for (i = 0; i < num_banks; i++) {
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int bank = num_banks - i - 1;
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unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
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unsigned int stat = status[i];
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stat &= enabled;
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if (!stat)
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continue;
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while (stat) {
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int bit = __ffs(stat);
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int line = bank * 8 + bit;
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int child_irq = irq_find_mapping(stmpe_gpio->domain,
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line);
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handle_nested_irq(child_irq);
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stat &= ~(1 << bit);
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}
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stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
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/* Edge detect register is not present on 801 */
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if (stmpe->partnum != STMPE801)
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stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
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+ i, status[i]);
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}
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return IRQ_HANDLED;
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}
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static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct stmpe_gpio *stmpe_gpio = d->host_data;
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if (!stmpe_gpio)
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return -EINVAL;
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irq_set_chip_data(irq, stmpe_gpio);
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irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
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handle_simple_irq);
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irq_set_nested_thread(irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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return 0;
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}
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static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
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{
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#ifdef CONFIG_ARM
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set_irq_flags(irq, 0);
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#endif
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
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.unmap = stmpe_gpio_irq_unmap,
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.map = stmpe_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
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struct device_node *np)
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{
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int base = 0;
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if (!np)
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base = stmpe_gpio->irq_base;
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stmpe_gpio->domain = irq_domain_add_simple(np,
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stmpe_gpio->chip.ngpio, base,
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&stmpe_gpio_irq_simple_ops, stmpe_gpio);
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if (!stmpe_gpio->domain) {
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dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
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return -ENOSYS;
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}
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return 0;
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}
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static int stmpe_gpio_probe(struct platform_device *pdev)
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{
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struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
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struct device_node *np = pdev->dev.of_node;
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struct stmpe_gpio_platform_data *pdata;
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struct stmpe_gpio *stmpe_gpio;
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int ret;
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int irq = 0;
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pdata = stmpe->pdata->gpio;
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irq = platform_get_irq(pdev, 0);
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stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
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if (!stmpe_gpio)
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return -ENOMEM;
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mutex_init(&stmpe_gpio->irq_lock);
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stmpe_gpio->dev = &pdev->dev;
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stmpe_gpio->stmpe = stmpe;
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stmpe_gpio->chip = template_chip;
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stmpe_gpio->chip.ngpio = stmpe->num_gpios;
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stmpe_gpio->chip.dev = &pdev->dev;
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#ifdef CONFIG_OF
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stmpe_gpio->chip.of_node = np;
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#endif
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stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
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if (pdata)
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stmpe_gpio->norequest_mask = pdata->norequest_mask;
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else if (np)
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of_property_read_u32(np, "st,norequest-mask",
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&stmpe_gpio->norequest_mask);
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if (irq >= 0)
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stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
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else
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dev_info(&pdev->dev,
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"device configured in no-irq mode; "
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"irqs are not available\n");
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ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
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if (ret)
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goto out_free;
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if (irq >= 0) {
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ret = stmpe_gpio_irq_init(stmpe_gpio, np);
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if (ret)
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goto out_disable;
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ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
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IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
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if (ret) {
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dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
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goto out_disable;
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}
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}
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ret = gpiochip_add(&stmpe_gpio->chip);
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if (ret) {
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dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
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goto out_freeirq;
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}
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if (pdata && pdata->setup)
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pdata->setup(stmpe, stmpe_gpio->chip.base);
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platform_set_drvdata(pdev, stmpe_gpio);
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return 0;
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out_freeirq:
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if (irq >= 0)
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free_irq(irq, stmpe_gpio);
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out_disable:
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stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
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out_free:
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kfree(stmpe_gpio);
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return ret;
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}
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static int stmpe_gpio_remove(struct platform_device *pdev)
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{
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struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
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int irq = platform_get_irq(pdev, 0);
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int ret;
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if (pdata && pdata->remove)
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pdata->remove(stmpe, stmpe_gpio->chip.base);
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ret = gpiochip_remove(&stmpe_gpio->chip);
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if (ret < 0) {
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dev_err(stmpe_gpio->dev,
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"unable to remove gpiochip: %d\n", ret);
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return ret;
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}
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stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
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if (irq >= 0)
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free_irq(irq, stmpe_gpio);
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kfree(stmpe_gpio);
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return 0;
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}
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static struct platform_driver stmpe_gpio_driver = {
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.driver.name = "stmpe-gpio",
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.driver.owner = THIS_MODULE,
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.probe = stmpe_gpio_probe,
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.remove = stmpe_gpio_remove,
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};
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static int __init stmpe_gpio_init(void)
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{
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return platform_driver_register(&stmpe_gpio_driver);
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}
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subsys_initcall(stmpe_gpio_init);
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static void __exit stmpe_gpio_exit(void)
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{
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platform_driver_unregister(&stmpe_gpio_driver);
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}
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module_exit(stmpe_gpio_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("STMPExxxx GPIO driver");
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MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
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