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6263b51eb3
The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: <stable@vger.kernel.org> # 4.9.x+ Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
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| .. | ||
| amcc | ||
| bcm | ||
| caam | ||
| cavium | ||
| ccp | ||
| chelsio | ||
| marvell | ||
| mediatek | ||
| nx | ||
| qat | ||
| qce | ||
| rockchip | ||
| stm32 | ||
| sunxi-ss | ||
| ux500 | ||
| virtio | ||
| vmx | ||
| atmel-aes-regs.h | ||
| atmel-aes.c | ||
| atmel-authenc.h | ||
| atmel-sha-regs.h | ||
| atmel-sha.c | ||
| atmel-tdes-regs.h | ||
| atmel-tdes.c | ||
| bfin_crc.c | ||
| bfin_crc.h | ||
| exynos-rng.c | ||
| geode-aes.c | ||
| geode-aes.h | ||
| hifn_795x.c | ||
| img-hash.c | ||
| ixp4xx_crypto.c | ||
| Kconfig | ||
| Makefile | ||
| mv_cesa.c | ||
| mv_cesa.h | ||
| mxc-scc.c | ||
| mxs-dcp.c | ||
| n2_asm.S | ||
| n2_core.c | ||
| n2_core.h | ||
| omap-aes.c | ||
| omap-des.c | ||
| omap-sham.c | ||
| padlock-aes.c | ||
| padlock-sha.c | ||
| picoxcell_crypto_regs.h | ||
| picoxcell_crypto.c | ||
| s5p-sss.c | ||
| sahara.c | ||
| talitos.c | ||
| talitos.h | ||