mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 06:26:38 +07:00
15f37e1588
Instead of rewriting the arguments to match the UHI spec, store the address of a appended or UHI supplied dtb in fw_supplied_dtb. That way the original bootloader arugments are kept intact while still making the use of an appended dtb invisible for mach code. Mach code can still find out if it is an appended dtb by comparing fw_arg1 with fw_supplied_dtb. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alban Bedel <albeu@free.fr> Cc: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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*/
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/bootmem.h>
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#include <linux/of_platform.h>
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#include <linux/of_fdt.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/prom.h>
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#include <lantiq.h>
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#include "prom.h"
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#include "clk.h"
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/* access to the ebu needs to be locked between different drivers */
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DEFINE_SPINLOCK(ebu_lock);
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EXPORT_SYMBOL_GPL(ebu_lock);
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/*
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* this struct is filled by the soc specific detection code and holds
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* information about the specific soc type, revision and name
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*/
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static struct ltq_soc_info soc_info;
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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}
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int ltq_soc_type(void)
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{
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return soc_info.type;
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}
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void __init prom_free_prom_memory(void)
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{
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}
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static void __init prom_init_cmdline(void)
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{
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int argc = fw_arg0;
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char **argv = (char **) KSEG1ADDR(fw_arg1);
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int i;
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arcs_cmdline[0] = '\0';
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for (i = 0; i < argc; i++) {
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char *p = (char *) KSEG1ADDR(argv[i]);
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if (CPHYSADDR(p) && *p) {
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strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
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strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
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}
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}
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}
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void __init plat_mem_setup(void)
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{
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void *dtb;
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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set_io_port_base((unsigned long) KSEG1);
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if (fw_passed_dtb) /* UHI interface */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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panic("no dtb found");
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/*
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* Load the devicetree. This causes the chosen node to be
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* parsed resulting in our memory appearing
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*/
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__dt_setup_arch(dtb);
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}
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void __init device_tree_init(void)
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{
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unflatten_and_copy_device_tree();
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}
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void __init prom_init(void)
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{
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/* call the soc specific detetcion code and get it to fill soc_info */
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ltq_soc_detect(&soc_info);
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snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
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soc_info.name, soc_info.rev_type);
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soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
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pr_info("SoC: %s\n", soc_info.sys_type);
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prom_init_cmdline();
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#if defined(CONFIG_MIPS_MT_SMP)
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if (register_vsmp_smp_ops())
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panic("failed to register_vsmp_smp_ops()");
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#endif
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}
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int __init plat_of_setup(void)
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{
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return __dt_register_buses(soc_info.compatible, "simple-bus");
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}
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arch_initcall(plat_of_setup);
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