mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 17:36:49 +07:00
a60514bae7
This defines __smp_xxx barriers for mips, for use by virtualization. smp_xxx barriers are removed as they are defined correctly by asm-generic/barriers.h Note: the only exception is smp_mb__before_llsc which is mips-specific. We define both the __smp_mb__before_llsc variant (for use in asm/barriers.h) and smp_mb__before_llsc (for use elsewhere on this architecture). Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
|
|
*/
|
|
#ifndef __ASM_BARRIER_H
|
|
#define __ASM_BARRIER_H
|
|
|
|
#include <asm/addrspace.h>
|
|
|
|
#ifdef CONFIG_CPU_HAS_SYNC
|
|
#define __sync() \
|
|
__asm__ __volatile__( \
|
|
".set push\n\t" \
|
|
".set noreorder\n\t" \
|
|
".set mips2\n\t" \
|
|
"sync\n\t" \
|
|
".set pop" \
|
|
: /* no output */ \
|
|
: /* no input */ \
|
|
: "memory")
|
|
#else
|
|
#define __sync() do { } while(0)
|
|
#endif
|
|
|
|
#define __fast_iob() \
|
|
__asm__ __volatile__( \
|
|
".set push\n\t" \
|
|
".set noreorder\n\t" \
|
|
"lw $0,%0\n\t" \
|
|
"nop\n\t" \
|
|
".set pop" \
|
|
: /* no output */ \
|
|
: "m" (*(int *)CKSEG1) \
|
|
: "memory")
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
|
# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
|
|
# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
|
|
|
|
# define fast_wmb() __syncw()
|
|
# define fast_rmb() barrier()
|
|
# define fast_mb() __sync()
|
|
# define fast_iob() do { } while (0)
|
|
#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
|
|
# define fast_wmb() __sync()
|
|
# define fast_rmb() __sync()
|
|
# define fast_mb() __sync()
|
|
# ifdef CONFIG_SGI_IP28
|
|
# define fast_iob() \
|
|
__asm__ __volatile__( \
|
|
".set push\n\t" \
|
|
".set noreorder\n\t" \
|
|
"lw $0,%0\n\t" \
|
|
"sync\n\t" \
|
|
"lw $0,%0\n\t" \
|
|
".set pop" \
|
|
: /* no output */ \
|
|
: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
|
|
: "memory")
|
|
# else
|
|
# define fast_iob() \
|
|
do { \
|
|
__sync(); \
|
|
__fast_iob(); \
|
|
} while (0)
|
|
# endif
|
|
#endif /* CONFIG_CPU_CAVIUM_OCTEON */
|
|
|
|
#ifdef CONFIG_CPU_HAS_WB
|
|
|
|
#include <asm/wbflush.h>
|
|
|
|
#define mb() wbflush()
|
|
#define iob() wbflush()
|
|
|
|
#else /* !CONFIG_CPU_HAS_WB */
|
|
|
|
#define mb() fast_mb()
|
|
#define iob() fast_iob()
|
|
|
|
#endif /* !CONFIG_CPU_HAS_WB */
|
|
|
|
#define wmb() fast_wmb()
|
|
#define rmb() fast_rmb()
|
|
|
|
#if defined(CONFIG_WEAK_ORDERING)
|
|
# ifdef CONFIG_CPU_CAVIUM_OCTEON
|
|
# define __smp_mb() __sync()
|
|
# define __smp_rmb() barrier()
|
|
# define __smp_wmb() __syncw()
|
|
# else
|
|
# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
|
|
# define __smp_rmb() __asm__ __volatile__("sync" : : :"memory")
|
|
# define __smp_wmb() __asm__ __volatile__("sync" : : :"memory")
|
|
# endif
|
|
#else
|
|
#define __smp_mb() barrier()
|
|
#define __smp_rmb() barrier()
|
|
#define __smp_wmb() barrier()
|
|
#endif
|
|
|
|
#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
|
|
#define __WEAK_LLSC_MB " sync \n"
|
|
#else
|
|
#define __WEAK_LLSC_MB " \n"
|
|
#endif
|
|
|
|
#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
|
|
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
|
#define smp_mb__before_llsc() smp_wmb()
|
|
#define __smp_mb__before_llsc() __smp_wmb()
|
|
/* Cause previous writes to become visible on all CPUs as soon as possible */
|
|
#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
|
|
".set arch=octeon\n\t" \
|
|
"syncw\n\t" \
|
|
".set pop" : : : "memory")
|
|
#else
|
|
#define smp_mb__before_llsc() smp_llsc_mb()
|
|
#define __smp_mb__before_llsc() smp_llsc_mb()
|
|
#define nudge_writes() mb()
|
|
#endif
|
|
|
|
#define __smp_mb__before_atomic() __smp_mb__before_llsc()
|
|
#define __smp_mb__after_atomic() smp_llsc_mb()
|
|
|
|
#include <asm-generic/barrier.h>
|
|
|
|
#endif /* __ASM_BARRIER_H */
|