mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 06:17:11 +07:00
a48e61de75
As of ac7c3e4ff4 ("compiler: enable CONFIG_OPTIMIZE_INLINING forcibly"),
inline functions are no longer annotated with '__always_inline', which
allows the compiler to decide whether inlining is really a good idea or
not. Although this is a great idea on paper, the reality is that AArch64
GCC prior to 9.1 has been shown to get confused when creating an
out-of-line copy of a function passing explicit 'register' variables
into an inline assembly block:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91111
It's not clear whether this is specific to arm64 or not but, for now,
ensure that all of our functions using 'register' variables are marked
as '__always_inline' so that the old behaviour is effectively preserved.
Hopefully other architectures are luckier with their compilers.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Will Deacon <will@kernel.org>
401 lines
11 KiB
C
401 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_ATOMIC_LSE_H
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#define __ASM_ATOMIC_LSE_H
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#define ATOMIC_OP(op, asm_op) \
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static inline void __lse_atomic_##op(int i, atomic_t *v) \
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{ \
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asm volatile( \
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" " #asm_op " %w[i], %[v]\n" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v)); \
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}
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ATOMIC_OP(andnot, stclr)
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ATOMIC_OP(or, stset)
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ATOMIC_OP(xor, steor)
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ATOMIC_OP(add, stadd)
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline int __lse_atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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" " #asm_op #mb " %w[i], %w[i], %[v]" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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#define ATOMIC_FETCH_OPS(op, asm_op) \
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ATOMIC_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC_FETCH_OPS(andnot, ldclr)
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ATOMIC_FETCH_OPS(or, ldset)
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ATOMIC_FETCH_OPS(xor, ldeor)
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ATOMIC_FETCH_OPS(add, ldadd)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_FETCH_OPS
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#define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \
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static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \
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{ \
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u32 tmp; \
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\
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asm volatile( \
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" ldadd" #mb " %w[i], %w[tmp], %[v]\n" \
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" add %w[i], %w[i], %w[tmp]" \
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: [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC_OP_ADD_RETURN(_relaxed, )
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ATOMIC_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC_OP_ADD_RETURN
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static inline void __lse_atomic_and(int i, atomic_t *v)
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{
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asm volatile(
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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: "r" (v));
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}
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#define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
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static inline int __lse_atomic_fetch_and##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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" mvn %w[i], %w[i]\n" \
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" ldclr" #mb " %w[i], %w[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC_FETCH_OP_AND(_relaxed, )
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ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC_FETCH_OP_AND(_release, l, "memory")
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ATOMIC_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC_FETCH_OP_AND
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static inline void __lse_atomic_sub(int i, atomic_t *v)
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{
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asm volatile(
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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: "r" (v));
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}
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#define ATOMIC_OP_SUB_RETURN(name, mb, cl...) \
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static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \
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{ \
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u32 tmp; \
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\
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asm volatile( \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[tmp], %[v]\n" \
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" add %w[i], %w[i], %w[tmp]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC_OP_SUB_RETURN(_relaxed, )
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ATOMIC_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC_OP_SUB_RETURN
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#define ATOMIC_FETCH_OP_SUB(name, mb, cl...) \
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static inline int __lse_atomic_fetch_sub##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC_FETCH_OP_SUB(_relaxed, )
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ATOMIC_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC_FETCH_OP_SUB
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#define ATOMIC64_OP(op, asm_op) \
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static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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" " #asm_op " %[i], %[v]\n" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v)); \
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}
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ATOMIC64_OP(andnot, stclr)
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ATOMIC64_OP(or, stset)
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ATOMIC64_OP(xor, steor)
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ATOMIC64_OP(add, stadd)
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#undef ATOMIC64_OP
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#define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline long __lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v)\
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{ \
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asm volatile( \
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" " #asm_op #mb " %[i], %[i], %[v]" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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#define ATOMIC64_FETCH_OPS(op, asm_op) \
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ATOMIC64_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC64_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC64_FETCH_OPS(andnot, ldclr)
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ATOMIC64_FETCH_OPS(or, ldset)
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ATOMIC64_FETCH_OPS(xor, ldeor)
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ATOMIC64_FETCH_OPS(add, ldadd)
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_FETCH_OPS
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#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...) \
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static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\
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{ \
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unsigned long tmp; \
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\
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asm volatile( \
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" ldadd" #mb " %[i], %x[tmp], %[v]\n" \
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" add %[i], %[i], %x[tmp]" \
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: [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC64_OP_ADD_RETURN(_relaxed, )
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ATOMIC64_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC64_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC64_OP_ADD_RETURN
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static inline void __lse_atomic64_and(s64 i, atomic64_t *v)
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{
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asm volatile(
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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: "r" (v));
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}
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#define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
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static inline long __lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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" mvn %[i], %[i]\n" \
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" ldclr" #mb " %[i], %[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC64_FETCH_OP_AND(_relaxed, )
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ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_AND(_release, l, "memory")
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ATOMIC64_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC64_FETCH_OP_AND
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static inline void __lse_atomic64_sub(s64 i, atomic64_t *v)
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{
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asm volatile(
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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: "r" (v));
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}
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#define ATOMIC64_OP_SUB_RETURN(name, mb, cl...) \
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static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v) \
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{ \
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unsigned long tmp; \
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\
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asm volatile( \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %x[tmp], %[v]\n" \
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" add %[i], %[i], %x[tmp]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC64_OP_SUB_RETURN(_relaxed, )
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ATOMIC64_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC64_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC64_OP_SUB_RETURN
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#define ATOMIC64_FETCH_OP_SUB(name, mb, cl...) \
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static inline long __lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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: cl); \
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\
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return i; \
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}
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ATOMIC64_FETCH_OP_SUB(_relaxed, )
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ATOMIC64_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC64_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC64_FETCH_OP_SUB
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static inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v)
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{
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unsigned long tmp;
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asm volatile(
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"1: ldr %x[tmp], %[v]\n"
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" subs %[ret], %x[tmp], #1\n"
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" b.lt 2f\n"
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" casal %x[tmp], %[ret], %[v]\n"
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" sub %x[tmp], %x[tmp], #1\n"
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" sub %x[tmp], %x[tmp], %[ret]\n"
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" cbnz %x[tmp], 1b\n"
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"2:"
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: [ret] "+&r" (v), [v] "+Q" (v->counter), [tmp] "=&r" (tmp)
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:
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: "cc", "memory");
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return (long)v;
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}
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#define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \
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static __always_inline u##sz \
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__lse__cmpxchg_case_##name##sz(volatile void *ptr, \
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u##sz old, \
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u##sz new) \
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{ \
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register unsigned long x0 asm ("x0") = (unsigned long)ptr; \
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register u##sz x1 asm ("x1") = old; \
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register u##sz x2 asm ("x2") = new; \
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unsigned long tmp; \
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\
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asm volatile( \
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" mov %" #w "[tmp], %" #w "[old]\n" \
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" cas" #mb #sfx "\t%" #w "[tmp], %" #w "[new], %[v]\n" \
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" mov %" #w "[ret], %" #w "[tmp]" \
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: [ret] "+r" (x0), [v] "+Q" (*(unsigned long *)ptr), \
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[tmp] "=&r" (tmp) \
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: [old] "r" (x1), [new] "r" (x2) \
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: cl); \
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\
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return x0; \
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}
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__CMPXCHG_CASE(w, b, , 8, )
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__CMPXCHG_CASE(w, h, , 16, )
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__CMPXCHG_CASE(w, , , 32, )
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__CMPXCHG_CASE(x, , , 64, )
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__CMPXCHG_CASE(w, b, acq_, 8, a, "memory")
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__CMPXCHG_CASE(w, h, acq_, 16, a, "memory")
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__CMPXCHG_CASE(w, , acq_, 32, a, "memory")
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__CMPXCHG_CASE(x, , acq_, 64, a, "memory")
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__CMPXCHG_CASE(w, b, rel_, 8, l, "memory")
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__CMPXCHG_CASE(w, h, rel_, 16, l, "memory")
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__CMPXCHG_CASE(w, , rel_, 32, l, "memory")
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__CMPXCHG_CASE(x, , rel_, 64, l, "memory")
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__CMPXCHG_CASE(w, b, mb_, 8, al, "memory")
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__CMPXCHG_CASE(w, h, mb_, 16, al, "memory")
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__CMPXCHG_CASE(w, , mb_, 32, al, "memory")
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__CMPXCHG_CASE(x, , mb_, 64, al, "memory")
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#undef __CMPXCHG_CASE
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#define __CMPXCHG_DBL(name, mb, cl...) \
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static __always_inline long \
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__lse__cmpxchg_double##name(unsigned long old1, \
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unsigned long old2, \
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unsigned long new1, \
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unsigned long new2, \
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volatile void *ptr) \
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{ \
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unsigned long oldval1 = old1; \
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unsigned long oldval2 = old2; \
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register unsigned long x0 asm ("x0") = old1; \
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register unsigned long x1 asm ("x1") = old2; \
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register unsigned long x2 asm ("x2") = new1; \
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register unsigned long x3 asm ("x3") = new2; \
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register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
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\
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asm volatile( \
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" casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
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" eor %[old1], %[old1], %[oldval1]\n" \
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" eor %[old2], %[old2], %[oldval2]\n" \
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" orr %[old1], %[old1], %[old2]" \
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: [old1] "+&r" (x0), [old2] "+&r" (x1), \
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[v] "+Q" (*(unsigned long *)ptr) \
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: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
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[oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
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: cl); \
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\
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return x0; \
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}
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__CMPXCHG_DBL( , )
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__CMPXCHG_DBL(_mb, al, "memory")
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#undef __CMPXCHG_DBL
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#endif /* __ASM_ATOMIC_LSE_H */
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